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A6.2.4 Data cache maintenance considerations

DC IVAC operations in AArch64 state are treated as DC CIVAC except for permission checking and

watchpoint matching.

DC ISW operations in AArch64 state, perform both a clean and invalidate of the target set/way. The

values of HCR.SWIO and HCR_EL2.SWIO have no effect.

See the Arm

Architecture Reference Manual Armv8, for Armv8-A architecture profile for more

information.

A6.2.5 Data cache coherency

To maintain data coherency between multiple cores, the Cortex-A76 core uses the MESI protocol.

A6.2.6 Write streaming mode

A cache line is allocated to the L1 on either a read miss or a write miss.

However, there are some situations where allocating on writes is not required. For example, when

executing the C standard library memset() function to clear a large block of memory to a known value.

Writes of large blocks of data can pollute the cache with unnecessary data. It can also waste power and

performance if a linefill must be performed only to discard the linefill data because the entire line was

subsequently written by the memset().

To counter this, the L1 memory system includes logic to detect when the core has stores pending to a full

cache line when it is waiting for a linefill to complete, or when it detects a DCZVA (full cache line write to

zero). If this situation is detected, then it switches into write streaming mode.

When in write streaming mode, loads behave as normal, and can still cause linefills, and writes still

lookup in the cache, but if they miss then they write out to L2 (or possibly L3, system cache, or DRAM)

rather than starting a linefill.

The L1 memory system continues in write streaming mode until it can no longer create a full cacheline

of store (for example because of a lack of resource in the L1 memory system) or has detected a high

proportion of store hitting in the cache.

Note

The L1 memory system is monitoring transaction traffic through L1 and, depending on different

thresholds, can set a stream to go out to L2, L3, and system cache and DRAM.

The following registers control the different thresholds:

AArch64 state

CPUECTLR_EL1 configure the L2, L3, and L4 write streaming mode threshold. See

B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1 on page B2-172.

A6 Level 1 memory system

A6.2 Cache behavior

reserved.

A6-74

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ARM Cortex-A76 Core Specifications

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