ARM Cortex-A76 Core User Manual

For any load or store that is targeted at a memory region that is marked as transient, the following occurs:
• If the memory access misses in the L1 data cache, the returned cache line is allocated in the L1 data
cache but is marked as transient.
• When the line is evicted from the L1 data cache, the transient hint is passed to the L2 cache so that
the replacement policy will not attempt to retain the line. When the line is subsequently evicted from
the L2 cache, it will bypass the L3 cache entirely.
Non-temporal loads
Non-temporal loads indicate to the caches that the data is likely to be used for only short periods. For
example, when streaming single-use read data that is then discarded. In addition to non-temporal loads,
there are also prefetch-memory (PRFM) hint instructions with the STRM qualifier.
Non-temporal loads to memory which are designated as Write-Back are treated the same as loads to
Transient memory.
A6.4.2 Internal exclusive monitor
The Cortex-A76 core L1 memory system has an internal exclusive monitor.
This monitor is a 2-state, open and exclusive, state machine that manages Load-Exclusive or Store-
Exclusive accesses and Clear-Exclusive (CLREX) instructions. You can use these instructions to construct
semaphores, ensuring synchronization between different processes running on the core, and also between
different cores that are using the same coherent memory locations for the semaphore. A Load-Exclusive
instruction tags a small block of memory for exclusive access. CTR.ERG defines the size of the tagged
block as 16 words, one cache line.
Note
A load/store exclusive instruction is any one of the following:
• In the A64 instruction set, any instruction that has a mnemonic starting with LDX, LDAX, STX, or STLX.
• In the A32 and T32 instruction sets, any instruction that has a mnemonic starting with LDREX, STREX,
LDAEX, or STLEX.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information about these instructions.
A6 Level 1 memory system
A6.4 L1 data memory system
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core