ARM Cortex-A76 Core User Manual

Table B2-5 Cluster registers (continued)
Name Copro CRn Opc1 CRm Opc2 Width Description
CLUSTERPMCLAIMSET_EL1 3 c15 0 c6 6 32-bit Cluster Performance Monitor Claim Tag Set
Register
CLUSTERPMCLAIMCLR_EL1 3 c15 0 c6 7 32-bit Cluster Performance Monitor Claim Tag Clear
Register
Security
Name Type Description
ACTLR_EL3 RW
B2.7 ACTLR_EL3, Auxiliary Control Register, EL3 on page B2-147
AFSR0_EL3 RW
B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3 on page B2-151
AFSR1_EL3 RW
B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3 on page B2-154
AMAIR_EL3 RW
B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3 on page B2-158
CPTR_EL3 RW
B2.22 CPTR_EL3, Architectural Feature Trap Register, EL3 on page B2-165
MDCR_EL3 RW
B2.83 MDCR_EL3, Monitor Debug Configuration Register, EL3 on page B2-264
Reset management registers
Name Type Description
RMR_EL3 RW
B2.88 RMR_EL3, Reset Management Register on page B2-271
RVBAR_EL3 RW
B2.89 RVBAR_EL3, Reset Vector Base Address Register, EL3 on page B2-272
Address registers
Name Type Description
PAR_EL1 RW
B2.86 PAR_EL1, Physical Address Register, EL1 on page B2-269
B2 AArch64 system registers
B2.4 AArch64 registers by functional group
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B2-143
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core