ARM Cortex-A76 Core User Manual

Threshold for direct stream to L4 cache on store. The possible values are:
00 16KB.
01 64KB. This is the reset value.
10 128KB.
11 Disables direct stream to L4 cache on store.
WS_THR_DRAM, [19:18]
Threshold for direct stream to DRAM on store. The possible values are:
00 64KB.
01 1MB, for memory designated as outer-allocate. This is the reset value.
10 1MB, allocating irrespective of outer-allocation designation.
11 Disables direct stream to DRAM on store.
WS_THR_DCZVA, [17]
Have DCZVA use a lower WS_THR_L2 configuration. The possible values are:
0 DCZVA behaves like normal store wrt WS_THR_L2.
1 DCZVA will use one lower stream threshold from WS_THR_L2. This is the reset
value.
RES0, [16]
RES0 Reserved.
PF_DIS, [15]
Disables data-side hardware prefetching. The possible values are:
0 Enables hardware prefetching. This is the reset value.
1 Disables hardware prefetching.
RES0, [14]
RES0 Reserved.
PF_SS_L2_DIST, [13:12]
Single cache line stride prefetching L2 distance. The possible values are:
00 22
01 28
10 34
11 40. This is the reset value.
RES0, [11:10]
RES0 Reserved.
RES0, [9]
RES0 Reserved.
PF_STI_DIS, [8]
Disables store prefetches at issue (not overriden by CPUECTLR_EL1[15]). The possible values
are:
0 Enables store prefetching. This is the reset value.
B2 AArch64 system registers
B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1
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B2-177
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core