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1 Disables store prefetching.

PF_STS_DIS, [7]

Disables store-stride prefetches. The possible values are:

0 Enables store prefetching. This is the reset value.

1 Disables store prefetching.

RES0, [6]

RES0 Reserved.

RPF_DIS, [5]

Disables region prefetcher. The possible values are:

0 Enables region prefetching. This is the reset value.

1 Disables region prefetching.

RPF_LO_CONF, [4]

Region prefetcher training behavior. The possible values are:

0 Limited training for region prefetcher on single accesses. This is the reset value.

1 Always train the region prefetcher on single accesses, which results in fewer prefetch

requests.

RPF_PHIT_EN, [3]

Enable region prefetcher propagation on hit. The possible values are:

0 Disables region prefetcher propagation on hit. This is the reset value.

1 Enables region prefetcher propagation on hit.

RES0, [2:1]

RES0 Reserved.

EXTLLC, [0]

Internal or external Last-level cache (LLC) in the system. The possible values are:

0 Indicates that an internal Last-level cache is present in the system, and that the

DataSource field on the master CHI interface indicates when data is returned from the

LLC. This is used to control how the LL_CACHE* PMU events count. This is the

reset value.

1 Indicates that an external Last-level cache is present in the system, and that the

DataSource field on the master CHI interface indicates when data is returned from the

LLC. This is used to control how the LL_CACHE* PMU events count.

Configurations

This register has no configuration options.

B2 AArch64 system registers

B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1

reserved.

B2-178

Non-Confidential

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ARM Cortex-A76 Core Specifications

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