ARM Cortex-A76 Core User Manual

Note
There are multiple asynchronous bridges between the Cortex-A76 core and the DSU. Only the CPU
bridge between the Cortex-A76 core and the DSU can be configured to run synchronously, however it
does not affect the other interfaces such as debug, trace, and GIC which are always asynchronous. For
more information on how to set the CPU bridge to run either synchronously or asynchronously, see
Configuration Guidelines in the Arm
®
DynamIQ
™
Shared Unit Configuration and Sign-off Guide.
A2.1.1 Instruction fetch
The instruction fetch unit fetches instructions from the L1 instruction cache and delivers the instruction
stream to the instruction decode unit.
The instruction fetch unit includes:
• A 64KB, 4-way, set associative L1 instruction cache with 64-byte cache lines and optional parity
protection.
• A fully associative L1 instruction TLB with native support for 4KB, 16KB, 64KB, 2MB, and 32MB
page sizes.
• A dynamic branch predictor.
A2.1.2 Instruction decode
The instruction decode unit supports the A32, T32, and A64 instruction sets. It also supports Advanced
SIMD and floating-point instructions in each instruction set.
A2.1.3 Register rename
The register rename unit performs register renaming to facilitate out-of-order execution and dispatches
decoded instructions to various issue queues.
A2.1.4 Instruction issue
The instruction issue unit controls when the decoded instructions are dispatched to the execution
pipelines. It includes issue queues for storing instruction pending dispatch to execution pipelines.
A2.1.5 Execution pipeline
The execution pipeline includes:
• Integer execute unit that performs arithmetic and logical data processing operations.
• Vector execute unit that performs Advanced SIMD and floating point operations. Optionally, it can
execute the cryptographic instructions.
A2.1.6 L1 data memory system
The L1 data memory system executes load and store instructions and encompasses the L1 data side
memory system. It also services memory coherency requests.
The load/store unit includes:
• A 64KB, 4-way, set associative L1 data cache with 64-byte cache lines and optional ECC protection
per 32 bits.
• A fully associative L1 data TLB with native support for 4KB, 16KB, 64KB, 2MB, and 512MB page
sizes.
A2.1.7 L2 memory system
The L2 memory system services L1 instruction and data cache misses from the Cortex-A76 core.
A2 Technical overview
A2.1 Components
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reserved.
A2-36
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core