ARM Cortex-A76 Core

The L2 memory system includes:
• An 8-way set associative L2 cache with data ECC protection per 64 bits. The L2 cache is
configurable with sizes of 128KB, 256KB, or 512KB.
• An interface with the DSU configurable at implementation time for synchronous or asynchronous
operation.
Related references
Chapter A5 Memory Management Unit on page A5-61
Chapter A6 Level 1 memory system on page A6-71
Chapter A7 Level 2 memory system on page A7-97
Chapter A9 Generic Interrupt Controller CPU interface on page A9-111
Chapter C1 Debug on page C1-365
Chapter C2 Performance Monitor Unit on page C2-371
Chapter C4 Embedded Trace Macrocell on page C4-391
A2 Technical overview
A2.1 Components
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A2-37
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