ARM Cortex-A76 Core User Manual

(continued)
Event
number
PMU
event bus
(to trace)
Event mnemonic Event description
0x20
[41:40] L2D_CACHE_ALLOCATE
L2 data cache allocation without refill. This event counts any full cache
line write into the L2 cache which does not cause a linefill, including
write-backs from L1 to L2 and full-line writes which do not allocate
into L1.
0x21
[42] BR_RETIRED
Instruction architecturally executed, branch. This event counts all
branches, taken or not. This excludes exception entries, debug entries
and CCFAIL branches.
0x22
[43] BR_MIS_PRED_RETIRED
Instruction architecturally executed, mispredicted branch. This event
counts any branch counted by BR_RETIRED which is not correctly
predicted and causes a pipeline flush.
0x23
[44] STALL_FRONTEND
No operation issued because of the frontend. The counter counts on any
cycle when there are no fetched instructions available to dispatch.
0x24
[45] STALL_BACKEND
No operation issued because of the backend. The counter counts on any
cycle fetched instructions are not dispatched due to resource
constraints.
0x25
[48:46] L1D_TLB
Level 1 data TLB access. This event counts any load or store operation
which accesses the data L1 TLB. If both a load and a store are executed
on a cycle, this event counts twice. This event counts regardless of
whether the MMU is enabled.
0x26
[168] L1I_TLB
Level 1 instruction TLB access. This event counts any instruction fetch
which accesses the instruction L1 TLB.This event counts regardless of
whether the MMU is enabled.
0x29
[157] L3D_CACHE_ALLOCATE Attributable L3 data or unified cache allocation without refill. This
event counts any full cache line write into the L3 cache which does not
cause a linefill, including write-backs from L2 to L3 and full-line
writes which do not allocate into L2.
0x2A
[159:158] L3D_CACHE_REFILL
Attributable Level 3 unified cache refill.
This event counts for any cacheable read transaction returning data
from the SCU for which the data source was outside the cluster.
Transactions such as ReadUnique are counted here as 'read'
transactions, even though they can be generated by store instructions.
0x2B
[160] L3D_CACHE
Attributable Level 3 unified cache access.
This event counts for any cacheable read transaction returning data
from the SCU, or for any cacheable write to the SCU.
0x2D
[49] L2D_TLB_REFILL
Attributable L2 data or unified TLB refill. This event counts on any
refill of the L2 TLB, caused by either an instruction or data access.
This event does not count if the MMU is disabled.
C2 Performance Monitor Unit
C2.3 PMU events
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reserved.
C2-377
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core