ARM Cortex-A76 Core User Manual

(continued)
Event
number
PMU
event bus
(to trace)
Event mnemonic Event description
0x2F
[51:50] L2D_TLB
Attributable L2 data or unified TLB access. This event counts on any
access to the L2 TLB (caused by a refill of any of the L1 TLBs). This
event does not count if the MMU is disabled.
0x31
[161] REMOTE_ACCESS Access to another socket in a multi-socket system.
0x34
[52] DTLB_WALK
Access to data TLB that caused a page table walk. This event counts on
any data access which causes L2D_TLB_REFILL to count.
0x35
[53] ITLB_WALK
Access to instruction TLB that caused a page table walk. This event
counts on any instruction access which causes L2D_TLB_REFILL to
count.
0x36
[163:162] LL_CACHE_RD Last level cache access, read.
• If CPUECTLR.EXTLLC is set: This event counts any cacheable
read transaction which returns a data source of 'interconnect cache'.
• If CPUECTLR.EXTLLC is not set: This event is a duplicate of the
L*D_CACHE_RD event corresponding to the last level of cache
implemented – L3D_CACHE_RD if both per-core L2 and cluster
L3 are implemented, L2D_CACHE_RD if only one is
implemented, or L1D_CACHE_RD if neither is implemented.
0x37
[165:164] LL_CACHE_MISS_RD Last level cache miss, read.
• If CPUECTLR.EXTLLC is set: This event counts any cacheable
read transaction which returns a data source of 'DRAM', 'remote' or
'inter-cluster peer'.
• If CPUECTLR.EXTLLC is not set: This event is a duplicate of the
L*D_CACHE_REFILL_RD event corresponding to the last level
of cache implemented – L3D_CACHE_REFILL_RD if both per-
core L2 and cluster L3 are implemented,
L2D_CACHE_REFILL_RD if only one is implemented, or
L1D_CACHE_REFILL_RD if neither is implemented.
0x40
[] L1D_CACHE_RD
L1 data cache access, read. This event counts any load operation or
page table walk access which looks up in the L1 data cache. In
particular, any access which could count the
L1D_CACHE_REFILL_RD event causes this event to count.
The following instructions are not counted:
• Cache maintenance instructions and prefetches.
• Non-cacheable accesses.
0x41
[57:56] L1D_CACHE_WR
L1 data cache access, write. This event counts any store operation
which looks up in the L1 data cache. In particular, any access which
could count the L1D_CACHE_REFILL_WR event causes this event to
count.
The following instructions are not counted:
• Cache maintenance instructions and prefetches.
• Non-cacheable accesses.
C2 Performance Monitor Unit
C2.3 PMU events
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reserved.
C2-378
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core