ARM Cortex-A76 Core User Manual

(continued)
Event
number
PMU
event bus
(to trace)
Event mnemonic Event description
0x42
[58] L1D_CACHE_REFILL_RD
L1 data cache refill, read. This event counts any load operation or page
table walk access which causes data to be read from outside the L1,
including accesses which do not allocate into L1.
The following instructions are not counted:
• Cache maintenance instructions and prefetches.
• Non-cacheable accesses.
0x43
[59] L1D_CACHE_REFILL_WR
L1 data cache refill, write. This event counts any store operation which
causes data to be read from outside the L1, including accesses which do
not allocate into L1.
The following instructions are not counted:
• Cache maintenance instructions and prefetches.
• Stores of an entire cache line, even if they make a coherency
request outside the L1.
• Partial cache line writes which do not allocate into the L1 cache.
• Non-cacheable accesses.
0x44
[60] L1D_CACHE_REFILL_INNER
L1 data cache refill, inner. This event counts any L1 D-cache linefill (as
counted by L1D_CACHE_REFILL) which hits in the L2 cache, L3
cache or another core in the cluster.
0x45
[61] L1D_CACHE_REFILL_OUTER
L1 data cache refill, outer. This event counts any L1 D-cache linefill (as
counted by L1D_CACHE_REFILL) which does not hit in the L2
cache, L3 cache or another core in the cluster, and instead obtains data
from outside the cluster.
0x46
[62] L1D_CACHE_WB_VICTIM L1 data cache write-back, victim
0x47
[63] L1D_CACHE_WB_CLEAN L1 data cache write-back cleaning and coherency
0x48
[64] L1D_CACHE_INVAL L1 data cache invalidate.
0x4C
[65] L1D_TLB_REFILL_RD L1 data TLB refill, read.
0x4D
[66] L1D_TLB_REFILL_WR L1 data TLB refill, write.
0x4E
[68:67] L1D_TLB_RD L1 data TLB access, read.
0x4F
[70:69] L1D_TLB_WR L1 data TLB access, write.
0x50
[72:71] L2D_CACHE_RD
L2 data cache access, read. This event counts any read transaction from
L1 which looks up in the L2 cache.
Snoops from outside the core are not counted.
0x51
[74:73] L2D_CACHE_WR
L2 data cache access, write. This event counts any write transaction
from L1 which looks up in the L2 cache or any write-back from L1
which allocates into the L2 cache.
Snoops from outside the core are not counted.
C2 Performance Monitor Unit
C2.3 PMU events
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reserved.
C2-379
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core