ARM Cortex-A76 Core User Manual

(continued)
Event
number
PMU
event bus
(to trace)
Event mnemonic Event description
0x52
[76:75] L2D_CACHE_REFILL_RD
L2 data cache refill, read. This event counts any cacheable read
transaction from L1 which causes data to be read from outside the core.
L2 refills caused by stashes into L2 should not be counted. Transactions
such as ReadUnique are counted here as 'read' transactions, even
though they can be generated by store instructions.
0x53
[78:77] L2D_CACHE_REFILL_WR
L2 data cache refill, write. This event counts any write transaction from
L1 which causes data to be read from outside the core. L2 refills caused
by stashes into L2 should not be counted. Transactions such as
ReadUnique are not counted as write transactions.
0x56
[80:79] L2D_CACHE_WB_VICTIM L2 data cache write-back, victim.
0x57
[82:81] L2D_CACHE_WB_CLEAN L2 data cache write-back, cleaning and coherency.
0x58
[84:83] L2D_CACHE_INVAL L2 data cache invalidate.
0x5C
[85] L2D_TLB_REFILL_RD L2 data or unified TLB refill, read.
0x5D
[86] L2D_TLB_REFILL_WR L2 data or unified TLB refill, write.
0x5E
[88:87] L2D_TLB_RD L2 data or unified TLB access, read.
0x5F
[89] L2D_TLB_WR L2 data or unified TLB access, write.
0x60
[90] BUS_ACCESS_RD
Bus access read. This event counts for every beat of data transferred
over the read data channel between the core and the SCU.
0x61
[91] BUS_ACCESS_WR
Bus access write. This event counts for every beat of data transferred
over the write data channel between the core and the SCU.
0x66
[93:92] MEM_ACCESS_RD
Data memory access, read. This event counts memory accesses due to
load instructions. The following instructions are not counted:
• Instruction fetches.
• Cache maintenance instructions.
• Translation table walks.
• Prefetches.
0x67
[95:94] MEM_ACCESS_WR
Data memory access, write. This event counts memory accesses due to
store instructions.
The following instructions are not counted:
• Instruction fetches.
• Cache maintenance instructions.
• Translation table walks.
• Prefetches.
0x68
[97:96] UNALIGNED_LD_SPEC Unaligned access, read
0x69
[99:98] UNALIGNED_ST_SPEC Unaligned access, write
0x6A
[102:100] UNALIGNED_LDST_SPEC Unaligned access
C2 Performance Monitor Unit
C2.3 PMU events
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
C2-380
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core