ARM Cortex-A76 Core User Manual

Table A-1 Armv8 Debug UNPREDICTABLE behaviors (continued)
Scenario Behavior
Accessing reserved debug registers
The core deviates from preferred behavior because the hardware cost to decode
some of these addresses in debug power domain is significantly high.
The actual behavior is:
1. For reserved debug registers in the address range 0x000-0xCFC and
Performance Monitors registers in the address range 0x000, the response is
either CONSTRAINED UNPREDICTABLE Error or RES0 when any of the following
errors occurs:
Off
The core power domain is either completely off or in a low-power
state where the core power domain registers cannot be accessed.
DLK
DoubleLockStatus() is TRUE and OS double-lock is locked
(EDPRSR.DLK is 1).
OSLK
OS lock is locked (OSLSR_EL1.OSLK is 1).
2. For reserved debug registers in the address ranges 0x400-0x4FC and
0x800-0x8FC, the response is CONSTRAINED UNPREDICTABLE Error or RES0
when the conditions in 1 do not apply and the following error occurs:
EDAD
AllowExternalDebugAccess() is FALSE. External debug
access is disabled.
3. For reserved Performance Monitor registers in the address ranges
0x000-0x0FC and 0x400-0x47C, the response is either CONSTRAINED
UNPREDICTABLE Error, or RES0 when the conditions in 1 and 2 do not apply,
and the following error occurs:
EPMAD
AllowExternalPMUAccess() is FALSE. External Performance
Monitors access is disabled.
Clearing the clear-after-read EDPRSR bits when
Core power domain is on, and
DoubleLockStatus() is TRUE
The core behaves as indicated in the sole Preference:
• Bits are not cleared to zero.
A Cortex
®
-A76 Core AArch32 unpredictable behaviors
A.3 Armv8 Debug UNPREDICTABLE behaviors
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core