ARM Cortex-A76 Core User Manual

Chapter A4 Power management
A4.1 About power management .................................................................................... A4-46
A4.2 Voltage domains .................................................................................................... A4-47
A4.3 Power domains .................................................. .................................................. A4-48
A4.4 Architectural clock gating modes ..................................... ..................................... A4-50
A4.5 Power control ........................................................................................................ A4-52
A4.6 Core power modes ................................................................................................ A4-53
A4.7 Encoding for power modes ......................................... ......................................... A4-56
A4.8 Power domain states for power modes ................................ ................................ A4-57
A4.9 Power up and down sequences ............................................................................ A4-58
A4.10 Debug over powerdown ........................................................................................ A4-59
Chapter A5 Memory Management Unit
A5.1 About the MMU .................................................. .................................................. A5-62
A5.2 TLB organization ................................................. ................................................. A5-64
A5.3 TLB match process ............................................... ............................................... A5-65
A5.4 Translation table walks .......................................................................................... A5-66
A5.5 MMU memory accesses ........................................................................................ A5-67
A5.6 Specific behaviors on aborts and memory attributes ............................................ A5-68
Chapter A6 Level 1 memory system
A6.1 About the L1 memory system ....................................... ....................................... A6-72
A6.2 Cache behavior .................................................. .................................................. A6-73
A6.3 L1 instruction memory system ....................................... ....................................... A6-75
A6.4 L1 data memory system ........................................................................................ A6-77
A6.5 Data prefetching .................................................................................................... A6-79
A6.6 Direct access to internal memory .......................................................................... A6-80
Chapter A7 Level 2 memory system
A7.1 About the L2 memory system ....................................... ....................................... A7-98
A7.2 About the L2 cache ............................................... ............................................... A7-99
A7.3 Support for memory types ......................................... ......................................... A7-100
Chapter A8 Reliability, Availability, and Serviceability (RAS)
A8.1 Cache ECC and parity ........................................................................................ A8-102
A8.2 Cache protection behavior ........................................ ........................................ A8-103
A8.3 Uncorrected errors and data poisoning ............................... ............................... A8-105
A8.4 RAS error types ................................................. ................................................. A8-106
A8.5 Error Synchronization Barrier ...................................... ...................................... A8-107
A8.6 Error recording .................................................................................................... A8-108
A8.7 Error injection ...................................................................................................... A8-109
Chapter A9 Generic Interrupt Controller CPU interface
A9.1 About the Generic Interrupt Controller CPU interface .................... .................... A9-112
A9.2 Bypassing the CPU interface ....................................... ....................................... A9-113
Chapter A10 Advanced SIMD and floating-point support
A10.1 About the Advanced SIMD and floating-point support ................... ................... A10-116
A10.2 Accessing the feature identification registers .................................................... A10-117
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core