ARM Cortex-A76 Core User Manual

Part B Register descriptions
Chapter B1 AArch32 system registers
B1.1 AArch32 architectural system register summary ........................ ........................ B1-122
Chapter B2 AArch64 system registers
B2.1 AArch64 registers ................................................................................................ B2-126
B2.2 AArch64 architectural system register summary ........................ ........................ B2-127
B2.3 AArch64 implementation defined register summary ..................... ..................... B2-134
B2.4 AArch64 registers by functional group ................................................................ B2-136
B2.5 ACTLR_EL1, Auxiliary Control Register, EL1 .......................... .......................... B2-144
B2.6 ACTLR_EL2, Auxiliary Control Register, EL2 .......................... .......................... B2-145
B2.7 ACTLR_EL3, Auxiliary Control Register, EL3 .......................... .......................... B2-147
B2.8 AFSR0_EL1, Auxiliary Fault Status Register 0, EL1 ..................... ..................... B2-149
B2.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2 ..................... ..................... B2-150
B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3 ..................... ..................... B2-151
B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1 ..................... ..................... B2-152
B2.12 AFSR1_EL2, Auxiliary Fault Status Register 1, EL2 ..................... ..................... B2-153
B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3 ..................... ..................... B2-154
B2.14 AIDR_EL1, Auxiliary ID Register, EL1 ................................................................ B2-155
B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1 .................... B2-156
B2.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2 .................... B2-157
B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3 .................... B2-158
B2.18 CCSIDR_EL1, Cache Size ID Register, EL1 ...................................................... B2-159
B2.19 CLIDR_EL1, Cache Level ID Register, EL1 ........................... ........................... B2-161
B2.20 CPACR_EL1, Architectural Feature Access Control Register, EL1 .................... B2-163
B2.21 CPTR_EL2, Architectural Feature Trap Register, EL2 ........................................ B2-164
B2.22 CPTR_EL3, Architectural Feature Trap Register, EL3 ........................................ B2-165
B2.23 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1 .................. .................. B2-166
B2.24 CPUACTLR2_EL1, CPU Auxiliary Control Register 2, EL1 ................................ B2-168
B2.25 CPUCFR_EL1, CPU Configuration Register, EL1 .............................................. B2-170
B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1 ................. ................. B2-172
B2.27 CPUPCR_EL3, CPU Private Control Register, EL3 ............................................ B2-180
B2.28 CPUPMR_EL3, CPU Private Mask Register, EL3 .............................................. B2-182
B2.29 CPUPOR_EL3, CPU Private Operation Register, EL3 ................... ................... B2-184
B2.30 CPUPSELR_EL3, CPU Private Selection Register, EL3 .................................... B2-186
B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1 ..................... ..................... B2-188
B2.32 CSSELR_EL1, Cache Size Selection Register, EL1 ..................... ..................... B2-190
B2.33 CTR_EL0, Cache Type Register, EL0 ................................ ................................ B2-191
B2.34 DCZID_EL0, Data Cache Zero ID Register, EL0 ................................................ B2-193
B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1 ..................... ..................... B2-194
B2.36 ERRIDR_EL1, Error ID Register, EL1 ................................ ................................ B2-196
B2.37 ERRSELR_EL1, Error Record Select Register, EL1 .......................................... B2-197
B2.38 ERXADDR_EL1, Selected Error Record Address Register, EL1 ........................ B2-198
B2.39 ERXCTLR_EL1, Selected Error Record Control Register, EL1 .......................... B2-199
B2.40 ERXFR_EL1, Selected Error Record Feature Register, EL1 .............................. B2-200
B2.41 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1 .......... B2-201
B2.42 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1 .......... B2-202
B2.43 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register,
EL1 ...................................................................................................................... B2-203
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core