ARM Cortex-A76 Core User Manual

B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1 ...
............................................................................................................................. B2-204
B2.45 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1 . . B2-206
B2.46 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1 .......... B2-207
B2.47 ESR_EL1, Exception Syndrome Register, EL1 ......................... ......................... B2-208
B2.48 ESR_EL2, Exception Syndrome Register, EL2 ......................... ......................... B2-209
B2.49 ESR_EL3, Exception Syndrome Register, EL3 ......................... ......................... B2-210
B2.50 HACR_EL2, Hyp Auxiliary Configuration Register, EL2 ...................................... B2-211
B2.51 HCR_EL2, Hypervisor Configuration Register, EL2 ............................................ B2-212
B2.52 ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0 ............... ............... B2-214
B2.53 ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1 ............... ............... B2-215
B2.54 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0, EL1 ............ ............ B2-216
B2.55 ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1, EL1 ............ ............ B2-218
B2.56 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1 ..... ..... B2-219
B2.57 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1, EL1 ..... ..... B2-221
B2.58 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1 .... .... B2-222
B2.59 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1 .... .... B2-224
B2.60 ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1 .... .... B2-226
B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1 .................... B2-227
B2.62 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1 .................... B2-229
B2.63 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0, EL1 ............... ............... B2-230
B2.64 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1 .................................. B2-231
B2.65 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1 .................... B2-233
B2.66 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1 .................... B2-235
B2.67 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1 .................... B2-237
B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1 .................... B2-239
B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1 .................... B2-241
B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1 .................... B2-243
B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1 .................... B2-245
B2.72 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1 .................. B2-246
B2.73 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1 .................. B2-248
B2.74 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1 .................. B2-250
B2.75 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1 .................. B2-252
B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1 .................. B2-254
B2.77 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1 .............. .............. B2-256
B2.78 ID_PFR1_EL1, AArch32 Processor Feature Register 1, EL1 .............. .............. B2-258
B2.79 ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1 .............. .............. B2-260
B2.80 LORC_EL1, LORegion Control Register, EL1 .................................................... B2-261
B2.81 LORID_EL1, LORegion ID Register, EL1 ............................. ............................. B2-262
B2.82 LORN_EL1, LORegion Number Register, EL1 ......................... ......................... B2-263
B2.83 MDCR_EL3, Monitor Debug Configuration Register, EL3 ................. ................. B2-264
B2.84 MIDR_EL1, Main ID Register, EL1 ...................................................................... B2-266
B2.85 MPIDR_EL1, Multiprocessor Affinity Register, EL1 ...................... ...................... B2-267
B2.86 PAR_EL1, Physical Address Register, EL1 ............................ ............................ B2-269
B2.87 REVIDR_EL1, Revision ID Register, EL1 ............................. ............................. B2-270
B2.88 RMR_EL3, Reset Management Register ............................................................ B2-271
B2.89 RVBAR_EL3, Reset Vector Base Address Register, EL3 ................. ................. B2-272
B2.90 SCTLR_EL1, System Control Register, EL1 ........................... ........................... B2-273
B2.91 SCTLR_EL2, System Control Register, EL2 ........................... ........................... B2-275
B2.92 SCTLR_EL3, System Control Register, EL3 ........................... ........................... B2-276
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core