ARM Cortex-A76 Core User Manual

B2.93 TCR_EL1, Translation Control Register, EL1 ...................................................... B2-278
B2.94 TCR_EL2, Translation Control Register, EL2 ...................................................... B2-279
B2.95 TCR_EL3, Translation Control Register, EL3 ...................................................... B2-280
B2.96 TTBR0_EL1, Translation Table Base Register 0, EL1 ........................................ B2-281
B2.97 TTBR0_EL2, Translation Table Base Register 0, EL2 ........................................ B2-282
B2.98 TTBR0_EL3, Translation Table Base Register 0, EL3 ................... ................... B2-283
B2.99 TTBR1_EL1, Translation Table Base Register 1, EL1 ........................................ B2-284
B2.100 TTBR1_EL2, Translation Table Base Register 1, EL2 ........................................ B2-285
B2.101 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2 .............. .............. B2-286
B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register ............... ............... B2-287
B2.103 VTCR_EL2, Virtualization Translation Control Register, EL2 .............................. B2-288
B2.104 VTTBR_EL2, Virtualization Translation Table Base Register, EL2 .......... .......... B2-289
Chapter B3 Error system registers
B3.1 Error system register summary ..................................... ..................................... B3-292
B3.2 ERR0ADDR, Error Record Address Register .......................... .......................... B3-293
B3.3 ERR0CTLR, Error Record Control Register ........................................................ B3-294
B3.4 ERR0FR, Error Record Feature Register ............................. ............................. B3-296
B3.5 ERR0MISC0, Error Record Miscellaneous Register 0 ........................................ B3-298
B3.6 ERR0MISC1, Error Record Miscellaneous Register 1 ........................................ B3-301
B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register ..... ..... B3-302
B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register .................... B3-303
B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register ........................ B3-305
B3.10 ERR0STATUS, Error Record Primary Status Register ................... ................... B3-307
Chapter B4 GIC registers
B4.1 CPU interface registers ........................................... ........................................... B4-313
B4.2 AArch64 physical GIC CPU interface system register summary ............ ............ B4-314
B4.3 ICC_AP0R0_EL1, Interrupt Controller Active Priorities Group 0 Register 0, EL1 ....
............................................................................................................................. B4-315
B4.4 ICC_AP1R0_EL1, Interrupt Controller Active Priorities Group 1 Register 0 EL1 B4-316
B4.5 ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0, EL1 .................... B4-317
B4.6 ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1, EL1 .................... B4-318
B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1 ............... ............... B4-319
B4.8 ICC_CTLR_EL3, Interrupt Controller Control Register, EL3 ............... ............... B4-321
B4.9 ICC_SRE_EL1, Interrupt Controller System Register Enable Register, EL1 ...... B4-323
B4.10 ICC_SRE_EL2, Interrupt Controller System Register Enable register, EL2 ... ... B4-324
B4.11 ICC_SRE_EL3, Interrupt Controller System Register Enable register, EL3 ... ... B4-326
B4.12 AArch64 virtual GIC CPU interface register summary ........................................ B4-328
B4.13 ICV_AP0R0_EL1, Interrupt Controller Virtual Active Priorities Group 0 Register 0,
EL1 ...................................................................................................................... B4-329
B4.14 ICV_AP1R0_EL1, Interrupt Controller Virtual Active Priorities Group 1 Register 0,
EL1 ...................................................................................................................... B4-330
B4.15 ICV_BPR0_EL1, Interrupt Controller Virtual Binary Point Register 0, EL1 .... .... B4-331
B4.16 ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point Register 1, EL1 .... .... B4-332
B4.17 ICV_CTLR_EL1, Interrupt Controller Virtual Control Register, EL1 .................... B4-333
B4.18 AArch64 virtual interface control system register summary ................................ B4-335
B4.19 ICH_AP0R0_EL2, Interrupt Controller Hyp Active Priorities Group 0 Register 0, EL2 ....
............................................................................................................................. B4-336
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core