ARM Cortex-A76 Core User Manual

B4.20 ICH_AP1R0_EL2, Interrupt Controller Hyp Active Priorities Group 1 Register 0, EL2 ....
............................................................................................................................. B4-337
B4.21 ICH_HCR_EL2, Interrupt Controller Hyp Control Register, EL2 ............ ............ B4-338
B4.22 ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control Register, EL2 .... B4-341
B4.23 ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2 ............. ............. B4-343
Chapter B5 Advanced SIMD and floating-point registers
B5.1 AArch64 register summary .................................................................................. B5-346
B5.2 FPCR, Floating-point Control Register ................................................................ B5-347
B5.3 FPSR, Floating-point Status Register ................................ ................................ B5-349
B5.4 MVFR0_EL1, Media and VFP Feature Register 0, EL1 ...................................... B5-351
B5.5 MVFR1_EL1, Media and VFP Feature Register 1, EL1 ...................................... B5-353
B5.6 MVFR2_EL1, Media and VFP Feature Register 2, EL1 ...................................... B5-355
B5.7 AArch32 register summary .................................................................................. B5-357
B5.8 FPSCR, Floating-Point Status and Control Register ..................... ..................... B5-358
Part C Debug descriptions
Chapter C1 Debug
C1.1 About debug methods ............................................ ............................................ C1-366
C1.2 Debug register interfaces .................................................................................... C1-367
C1.3 Debug events ...................................................................................................... C1-369
C1.4 External debug interface .......................................... .......................................... C1-370
Chapter C2 Performance Monitor Unit
C2.1 About the PMU .................................................................................................... C2-372
C2.2 PMU functional description ........................................ ........................................ C2-373
C2.3 PMU events ........................................................................................................ C2-374
C2.4 PMU interrupts .................................................................................................... C2-383
C2.5 Exporting PMU events ........................................................................................ C2-384
Chapter C3 Activity Monitor Unit
C3.1 About the AMU .................................................................................................... C3-386
C3.2 Accessing the activity monitors ..................................... ..................................... C3-387
C3.3 AMU counters .................................................. .................................................. C3-388
C3.4 AMU events ........................................................................................................ C3-389
Chapter C4 Embedded Trace Macrocell
C4.1 About the ETM .................................................................................................... C4-392
C4.2 ETM trace unit generation options and resources .............................................. C4-393
C4.3 ETM trace unit functional description .................................................................. C4-395
C4.4 Resetting the ETM .............................................................................................. C4-396
C4.5 Programming and reading ETM trace unit registers ..................... ..................... C4-397
C4.6 ETM trace unit register interfaces ................................... ................................... C4-398
C4.7 Interaction with the PMU and Debug .................................................................. C4-399
Part D Debug registers
Chapter D1 AArch32 debug registers
D1.1 AArch32 debug register summary ................................... ................................... D1-404
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core