ARM Cortex-A76 Core User Manual

Chapter D2 AArch64 debug registers
D2.1 AArch64 debug register summary ................................... ................................... D2-406
D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1 .............................. D2-408
D2.3 DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1 ............... ............... D2-411
D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1 ............................ D2-412
Chapter D3 Memory-mapped debug registers
D3.1 Memory-mapped debug register summary ............................ ............................ D3-416
D3.2 EDCIDR0, External Debug Component Identification Register 0 ........... ........... D3-420
D3.3 EDCIDR1, External Debug Component Identification Register 1 ........... ........... D3-421
D3.4 EDCIDR2, External Debug Component Identification Register 2 ........... ........... D3-422
D3.5 EDCIDR3, External Debug Component Identification Register 3 ........... ........... D3-423
D3.6 EDDEVID, External Debug Device ID Register 0 ....................... ....................... D3-424
D3.7 EDDEVID1, External Debug Device ID Register 1 ...................... ...................... D3-425
D3.8 EDPIDR0, External Debug Peripheral Identification Register 0 .......................... D3-426
D3.9 EDPIDR1, External Debug Peripheral Identification Register 1 .......................... D3-427
D3.10 EDPIDR2, External Debug Peripheral Identification Register 2 .......................... D3-428
D3.11 EDPIDR3, External Debug Peripheral Identification Register 3 .......................... D3-429
D3.12 EDPIDR4, External Debug Peripheral Identification Register 4 .......................... D3-430
D3.13 EDPIDRn, External Debug Peripheral Identification Registers 5-7 .......... .......... D3-431
D3.14 EDRCR, External Debug Reserve Control Register ..................... ..................... D3-432
Chapter D4 AArch32 PMU registers
D4.1 AArch32 PMU register summary .................................... .................................... D4-434
D4.2 PMCEID0, Performance Monitors Common Event Identification Register 0 ...... D4-436
D4.3 PMCEID1, Performance Monitors Common Event Identification Register 1 ...... D4-439
D4.4 PMCR, Performance Monitors Control Register ........................ ........................ D4-441
Chapter D5 AArch64 PMU registers
D5.1 AArch64 PMU register summary .................................... .................................... D5-446
D5.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0 ..
............................................................................................................................. D5-448
D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0 ..
............................................................................................................................. D5-451
D5.4 PMCR_EL0, Performance Monitors Control Register, EL0 ................ ................ D5-453
Chapter D6 Memory-mapped PMU registers
D6.1 Memory-mapped PMU register summary ............................. ............................. D6-456
D6.2 PMCFGR, Performance Monitors Configuration Register .................................. D6-460
D6.3 PMCIDR0, Performance Monitors Component Identification Register 0 ............ D6-461
D6.4 PMCIDR1, Performance Monitors Component Identification Register 1 ............ D6-462
D6.5 PMCIDR2, Performance Monitors Component Identification Register 2 ............ D6-463
D6.6 PMCIDR3, Performance Monitors Component Identification Register 3 ............ D6-464
D6.7 PMPIDR0, Performance Monitors Peripheral Identification Register 0 ....... ....... D6-465
D6.8 PMPIDR1, Performance Monitors Peripheral Identification Register 1 ....... ....... D6-466
D6.9 PMPIDR2, Performance Monitors Peripheral Identification Register 2 ....... ....... D6-467
D6.10 PMPIDR3, Performance Monitors Peripheral Identification Register 3 ....... ....... D6-468
D6.11 PMPIDR4, Performance Monitors Peripheral Identification Register 4 ....... ....... D6-469
D6.12 PMPIDRn, Performance Monitors Peripheral Identification Register 5-7 ..... ..... D6-470
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core