ARM Cortex-A76 Core User Manual

Chapter D7 PMU snapshot registers
D7.1 PMU snapshot register summary ........................................................................ D7-472
D7.2 PMPCSSR, Snapshot Program Counter Sample Register ................ ................ D7-473
D7.3 PMCIDSSR, Snapshot CONTEXTIDR_EL1 Sample Register ............. ............. D7-474
D7.4 PMCID2SSR, Snapshot CONTEXTIDR_EL2 Sample Register ............ ............ D7-475
D7.5 PMSSSR, PMU Snapshot Status Register ............................ ............................ D7-476
D7.6 PMOVSSR, PMU Overflow Status Snapshot Register ................... ................... D7-477
D7.7 PMCCNTSR, PMU Cycle Counter Snapshot Register ................... ................... D7-478
D7.8 PMEVCNTSRn, PMU Cycle Counter Snapshot Registers 0-5 ............. ............. D7-479
D7.9 PMSSCR, PMU Snapshot Capture Register ...................................................... D7-480
Chapter D8 AArch64 AMU registers
D8.1 AArch64 AMU register summary .................................... .................................... D8-482
D8.2 AMCNTENCLR0_EL0, Activity Monitors Count Enable Clear Register, EL0 .. .. D8-483
D8.3 AMCNTENSET_EL0, Activity Monitors Count Enable Set Register, EL0 ..... ..... D8-484
D8.4 AMCFGR_EL0, Activity Monitors Configuration Register, EL0 ............. ............. D8-485
D8.5 AMUSERENR_EL0, Activity Monitor EL0 Enable access, EL0 .......................... D8-487
D8.6 AMEVCNTRn_EL0, Activity Monitor Event Counter Register, EL0 .......... .......... D8-489
D8.7 AMEVTYPERn_EL0, Activity Monitor Event Type Register, EL0 ........... ........... D8-490
Chapter D9 ETM registers
D9.1 ETM register summary ........................................................................................ D9-495
D9.2 TRCACATRn, Address Comparator Access Type Registers 0-7 ........................ D9-499
D9.3 TRCACVRn, Address Comparator Value Registers 0-7 .................. .................. D9-501
D9.4 TRCAUTHSTATUS, Authentication Status Register ..................... ..................... D9-502
D9.5 TRCAUXCTLR, Auxiliary Control Register ............................ ............................ D9-503
D9.6 TRCBBCTLR, Branch Broadcast Control Register ...................... ...................... D9-505
D9.7 TRCCCCTLR, Cycle Count Control Register .......................... .......................... D9-506
D9.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0 ............. ............. D9-507
D9.9 TRCCIDCVR0, Context ID Comparator Value Register 0 ................. ................. D9-508
D9.10 TRCCIDR0, ETM Component Identification Register 0 ...................................... D9-509
D9.11 TRCCIDR1, ETM Component Identification Register 1 ...................................... D9-510
D9.12 TRCCIDR2, ETM Component Identification Register 2 ...................................... D9-511
D9.13 TRCCIDR3, ETM Component Identification Register 3 ...................................... D9-512
D9.14 TRCCLAIMCLR, Claim Tag Clear Register ........................................................ D9-513
D9.15 TRCCLAIMSET, Claim Tag Set Register ............................................................ D9-514
D9.16 TRCCNTCTLR0, Counter Control Register 0 .......................... .......................... D9-515
D9.17 TRCCNTCTLR1, Counter Control Register 1 .......................... .......................... D9-517
D9.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1 ................. ................. D9-519
D9.19 TRCCNTVRn, Counter Value Registers 0-1 ........................... ........................... D9-520
D9.20 TRCCONFIGR, Trace Configuration Register .................................................... D9-521
D9.21 TRCDEVAFF0, Device Affinity Register 0 ............................. ............................. D9-524
D9.22 TRCDEVAFF1, Device Affinity Register 1 ............................. ............................. D9-526
D9.23 TRCDEVARCH, Device Architecture Register .................................................... D9-527
D9.24 TRCDEVID, Device ID Register .......................................................................... D9-528
D9.25 TRCDEVTYPE, Device Type Register ................................................................ D9-529
D9.26 TRCEVENTCTL0R, Event Control 0 Register .................................................... D9-530
D9.27 TRCEVENTCTL1R, Event Control 1 Register .................................................... D9-532
D9.28 TRCEXTINSELR, External Input Select Register ....................... ....................... D9-533
D9.29 TRCIDR0, ID Register 0 .......................................... .......................................... D9-534
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ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core