ARM Cortex-A76 Core

Table A6-4 L1 BTB data location encoding
Bit fields of Rd Description
[31:24] RAMID = 0x02
[23:20] Reserved
[19:18] Way
[17:15] Reserved
[14:5] Index [14:5]
[4:0] Reserved
Table A6-5 L1 GHB data location encoding
Bit fields of Rd Description
[31:24] RAMID = 0x03
[23:14] Reserved
[13:4] Index [13:4]
[3:0] Reserved
Table A6-6 L1 instruction TLB data location encoding
Bit fields of Rd Description
[31:24] RAMID = 0x04
[23:8] Reserved
[7:0] TLB Entry (<=47)
Table A6-7 BPIQ data location encoding
Bit fields of Rd Description
[31:24] RAMID = 0x05
[23:10] Reserved
[9:4] Index [5:0]
[3:0] Reserved
The following table shows the data that is returned from accessing the L1 instruction tag RAM.
A6 Level 1 memory system
A6.6 Direct access to internal memory
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
A6-81
Non-Confidential