ARM Cortex-A76 Core

Table A6-31 L2 TLB format (continued)
Register Bit field Description
Instruction Register 1 [63:54]
VMID [9:0]
[53:38] ASID [15:0]
[37] Walk cache entry
[36] Prefetched translation
[35:7] Virtual address [48:20]
[6] Non-secure
[5:0] Reserved
Instruction Register 2 [63:8]
Reserved
[7:6]
Translation regime:
00 Secure EL1
01 EL3
10 Non-secure EL1
11 EL2
[5:0] VMID [15:10]
A6 Level 1 memory system
A6.6 Direct access to internal memory
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