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ARM Cortex-A76 Core

ARM Cortex-A76 Core
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Table A6-31 L2 TLB format
Register Bit field Description
Instruction Register 0 [63:59]
Reserved
[58] Non-global
[57] Outer-shared
[56] Inner-shared
[55] Reserved
[54:52]
Memory attributes:
000 Device nGnRnE
001 Device nGnRE
010 Device nGRE
011 Device GRE
100 Non-cacheable
101 Write-Back No-Allocate
110 Write-Back Transient
111 Write-Back Read-Allocate and
Write-Allocate
[51:48]
Reserved
[47:20] Physical address [39:12]
[19:17]
Page size:
000 4KB
001 16KB
010 64KB
011 256KB
100 2MB
101 32MB
110 512MB
111 1GB
[16:7] Reserved
[6] Indicates that the entry is coalesced and
holds translations for four contiguous
pages
[5:2] This bit field contains the valid bits for
four contiguous pages. If the entry is non-
coalesced, then 0b0001 indicates a valid
entry.
[1:0] Reserved
A6 Level 1 memory system
A6.6 Direct access to internal memory
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
A6-94
Non-Confidential

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