ARM Cortex-A76 Core User Manual

Table A6-31 L2 TLB format
Register Bit field Description
Instruction Register 0 [63:59]
Reserved
[58] Non-global
[57] Outer-shared
[56] Inner-shared
[55] Reserved
[54:52]
Memory attributes:
000 Device nGnRnE
001 Device nGnRE
010 Device nGRE
011 Device GRE
100 Non-cacheable
101 Write-Back No-Allocate
110 Write-Back Transient
111 Write-Back Read-Allocate and
Write-Allocate
[51:48]
Reserved
[47:20] Physical address [39:12]
[19:17]
Page size:
000 4KB
001 16KB
010 64KB
011 256KB
100 2MB
101 32MB
110 512MB
111 1GB
[16:7] Reserved
[6] Indicates that the entry is coalesced and
holds translations for four contiguous
pages
[5:2] This bit field contains the valid bits for
four contiguous pages. If the entry is non-
coalesced, then 0b0001 indicates a valid
entry.
[1:0] Reserved
A6 Level 1 memory system
A6.6 Direct access to internal memory
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A6-94
Non-Confidential

ARM Cortex-A76 Core Specifications

General

Architecture	ARMv8.2-A
Microarchitecture	Cortex-A76
Pipeline Depth	13 stages
Frequency	Up to 3.0 GHz
Process Technology	7nm
Core Type	Out-of-order
NEON	Yes
Power Efficiency	Improved over Cortex-A75
Performance Improvement	35% over Cortex-A75
Core Count	1-4 cores per cluster
ISA Support	AArch64 and AArch32
Branch Prediction	Yes
L1 Data Cache	32KB, per core
L2 Cache	256KB or 512KB, per core
L3 Cache	Up to 4MB
Memory Support	LPDDR4, LPDDR4X, DDR4
DynamIQ Shared Unit (DSU)	DynamIQ Shared Unit (DSU)
Cryptography Extensions	Yes
Virtualization Support	Yes
L1 Cache	64 KB per core