ARM Cortex-A76 Core

Table A6-29 L2 victim format (continued)
Register Bit field Description
Data Register 1 [63:0] 0
Data Register 2 [63:0] 0
A6.6.4 Encoding for the L2 TLB
The following section describes the encoding for L2 TLB direct accesses.
The following table shows the encoding that is required to select a given TLB entry.
Table A6-30 L2 TLB encoding
Bit fields of Rd Description
[31:24] RAMID = 0x18
[23:21] Reserved
[20:18] Way
000 way0
001 way1
010 way2
011 way3
100 way4
[17:8] Reserved
[7:0] Index
The following table shows the data that is returned from accessing the L2 TLB.
A6 Level 1 memory system
A6.6 Direct access to internal memory
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