Table A6-27 L2 tag format with a 512KB L2 cache size
Register Bit field Description
Data Register 0
[63:43]
0
[42:36] ECC [6:0] if configured with ECC for a
512KB L2 cache size, otherwise 0
[35:12] Physical address [39:16]
[11] Non-secure identifier for the physical
address
[10:9] Virtual index [13:12]
[8:6] Reserved
[5] Shareable
[4] Outer allocation hint
[3] L1 data cache valid
[2:0]
L2 State
101 Modified
001 Exclusive
x11 Shared
xx0 Invalid
Data Register 1 [63:0] 0
Data Register 2 [63:0] 0
The following table shows the data that is returned from accessing the L2 data RAM.
Table A6-28 L2 data format
Register Bit field Description
Data Register 0 [63:0] Data [63:0]
Data Register 1 [63:0] Data [127:64]
Data Register 2 [63:16] 0
[15:8] ECC for Data [127:64] if configured with
ECC
[7:0] ECC for Data [63:0] if configured with
ECC
The following table shows the data that is returned from accessing the L2 victim RAM.
Table A6-29 L2 victim format
Register Bit field Description
Data Register 0 [63:7] 0
[6:0] PLRU [6:0]
A6 Level 1 memory system
A6.6 Direct access to internal memory
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
A6-92
Non-Confidential
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