ARM Cortex-A76 Core

Table A6-11 L1 GHB cache format
Register Bit field Description
Instruction Register 0 [63:0] Data [63:0]
Instruction Register 1 [63:32] 0
[31:0] Data [95:64]
Instruction Register 2 [63:0] 0
The following table shows the data that is returned from accessing the L1 instruction TLB RAM.
A6 Level 1 memory system
A6.6 Direct access to internal memory
100798_0300_00_en Copyright © 2016–2018 Arm Limited or its affiliates. All rights
reserved.
A6-83
Non-Confidential