Table A6-12 L1 instruction TLB cache format
Register Bit field Description
Instruction Register 0 [63:59]
Virtual address [16:12]
[58:56] TLB attribute
[55:53]
Memory attributes:
000 Device nGnRnE
001 Device nGnRE
010 Device nGRE
011 Device GRE
100 Non-cacheable
101 Write-Back No-Allocate
110 Write-Back Transient
111 Write-Back Read-Allocate and
Write-Allocate
[52:50]
Page size:
000 4KB
001 16KB
010 64KB
011 256KB
100 2MB
101 32MB
11x Reserved
[49:46] TLB attribute
[45] Outer-shared
[44] Inner-shared
[43:39] TLB attribute
[38:23] ASID
[22:7] VMID
[6:5]
Translation regime:
00 Secure EL1/EL0
01 Secure EL3
10 Non-secure EL1/EL0
11 Non-secure EL2
[4:1] TLB attribute
[0] Valid
Instruction Register 1 [60]
Non-secure
[59:32] Physical address [39:12]
[31:0] Virtual address[48:17]
A6 Level 1 memory system
A6.6 Direct access to internal memory
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reserved.
A6-84
Non-Confidential
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