ARM Cortex-A76 Core

Table A6-22 L2 tag location encoding
Bit fields of Rd Description
[31:24] RAMID = 0x10
[23:21] Reserved
[20:18] Way (0->7)
[17:16] Reserved
[15:6] Index[15:6]
[5:0] Reserved
Table A6-23 L2 data location encoding
Bit fields of Rd Description
[31:24] RAMID = 0x11
[23:21] Reserved
[20:18] Way (0->7)
[17:16] Reserved
[15:4] Index[15:4]
[3:0] Reserved
Table A6-24 L2 victim location encoding
Bit fields of Rd Description
[31:24] RAMID = 0x12
[23:16] Reserved
[15:6] Index[15:6]
[5:0] Reserved
The following table shows the data that is returned from accessing the L2 tag RAM when L2 is
configured with a 128KB cache size.
A6 Level 1 memory system
A6.6 Direct access to internal memory
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