ARM Cortex-A76 Core

Table A6-25 L2 tag format with a 128KB L2 cache size
Register Bit field Description
Data Register 0
[63:45]
0
[44:38] ECC [6:0] if configured with ECC for a
128KB L2 cache size, otherwise 0
[37:12] Physical address [39:14]
[11] Non-secure identifier for the physical
address
[10:9] Virtual index [13:12]
[8:6] Reserved
[5] Shareable
[4] Outer allocation hint
[3] L1 data cache valid
[2:0]
L2 State
101 Modified
001 Exclusive
x11 Shared
xx0 Invalid
Data Register 1 [63:0] 0
Data Register 2 [63:0] 0
The following table shows the data that is returned from accessing the L2 tag RAM when L2 is
configured with a 256KB cache size.
A6 Level 1 memory system
A6.6 Direct access to internal memory
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