Sel 411L - Page 1099

IN.9Index
U–Z
Date Code 20151029 SEL-411L Relay
Timeout
front panel
P.7.3
serial port
C.2.8
Time-Overcurrent Curves
P.3.207–
P.3.209
Timers
See SEL
OGIC Control Equations
Time-Synchronized Measurements
P. 13 . 1–P.13.11
See also Synchrophasors
time trigger P. 1 3. 8–P.13.11
application example
P. 1 3. 8 –
P.13.11
Trigger
data capture
P.8.4
event
P.8 .4
PMU
C.6.13
TRIGGER Command
P.1 5.62
Trip
output
P.2.35, P.1 0.24
Relay Word bit, TRIP
P.8.4
Trip Bus
capture external/internal trips
P.9.7
Trip Logic
P.3.237–P.3.247
logic diagrams
P.3.242–P.3.247
manual trip
P.3.240
single-pole tripping
P.3.237
three-pole tripping
P.3.237
trip equations
P.3.238
DTA, DTB, DTC
P.3.239
TR
P.3.238
TRCOMM
P.3.239
TRSOTF
P.3.239
trip Relay Word bits
P.3.240
trip timers
P.3.239
TDUR1D and TDUR3D
P.3.239
TOPD
P.3.240
trip unlatch options
P.3.239
TULO
P.3.239
ULTR
P.3.239
Troubleshooting
P.1 1.43 –P.11.45
U
UCA2 C.5.3
GOOSE
C.5.5
Underfrequency Elements
P.3.257
User Interface
Telnet access
C.1.12
V
VERSION Command P.1 5.63 –P.15.6 4
firmware number
P.11. 39
release numbers
P.15.63
sample response
P.15.63
Virtual Devices P.15.58
Virtual File Interface
C.1.13–C.1.16
Voltage Checks
autoreclose
P. 4. 4 2
W
Wire
grounding size
P.2 .3 0
insulation
P.2.25
power connection size
P. 2. 32 , P.10.3
Z
Zero-Sequence Current Compensation
P.3.178, P.3.183
Zone Time Delay
P.3.197–P.3.199
common timing
P.3.198
independent timing
P.3.197
logic diagram
P.3.199