Sel 411L - Figure 3.198 Quality of Synchronization Logic (P-Th Channel); Figure 3.199 Quality of Synchronization Logic (87 L Scheme); Table 3.153 Channel Synchronization Method Relay Word Bits

P.3.290
SEL-411L Relay Protection Manual Date Code 20151029
Protection Functions
87L Channel Synchronization Logic and Status
If any of the required channels (87CHpRQ asserted) exhibits low
synchronization quality (87CHpLS asserted), the relay declares that the 87L
system has low synchronization.
If all required channels exhibit high synchronization quality (87CHpHS
asserted), the relay declares that the 87L system has high synchronization
quality. If stub bus is asserted, no channel is required, and the relay declares
high synchronization quality.
Figure 3.198 Quality of Synchronization Logic (p-th Channel)
Figure 3.199 Quality of Synchronization Logic (87L Scheme)
The 87SYNL bit feeds into the setting switch-over logic (87LPSEC,
87LQSEC, and 87LGSEC), forcing the application of extended security
settings for the Alpha Plane (see 87L Differential Elements).
The relay multi-ended fault locator reverts to a single-ended method if
synchronization is insufficiently precise.
Table 3.153 Channel Synchronization Method Relay Word Bits (Sheet 1 of 2)
Name Description
87CH1CS Channel-based synchronization in effect for the 87L Channel 1 (serial
channels only)
87CH2CS Channel-based synchronization in effect for the 87L Channel 2 (serial
channels only)
87CH1TS External time-based synchronization in effect for the 87L Channel 1
87CH2TS External time-based synchronization in effect for the 87L Channel 2
87CHpLS
87CHpHS
87CHpCH
87CHpCS
87CHpCL
87CHpFC
87CHpTS
Relay
Word Bits
Relay
Word Bits
0.5 s
0
0.5 s
0
87SYNL
87CHpRQ
87CHpLS
Relay
Word Bits
87CHpRQ
87CHpHS
All required
channels
SEL
OGIC
ESTUB
All required
channels
Relay
Word Bits
Relay
Word Bits
Relay
Word Bits
87SYNH