Sel 411L - Figure 3.94 Load-Encroachment Logic Diagram; Load-Encroachment Logic; Table 3.84 Series-Compensation Line Logic Relay Settings

P.3.156
SEL-411L Relay Protection Manual Date Code 20151029
Protection Functions
Load-Encroachment Logic
For more information on setting the relay for series-compensated lines see
SEL Application Guide 2000-11: Applying the SEL-321 Relay on Series-
Compensated Systems.
Load-Encroachment Logic
The load-encroachment logic prevents load from causing phase protection to
operate. You can set the phase distance and phase overcurrent elements
independent of load. Two independent positive-sequence impedance
characteristics monitor the positive-sequence load impedance (Z
1
) for both
export and import load. The positive-sequence voltage-polarized directional
element (32P) is blocked when the load-encroachment logic is enabled and
load is detected. The phase distance elements cannot operate during balanced
system conditions unless the logic asserts the 32P element.
Figure 3.94 illustrates the load-encroachment logic. The logic operates only if
the positive-sequence current (I
1
) is greater than the positive-sequence
threshold (10 percent of the nominal relay current). Relay Word bit ZLOUT
indicates that load is flowing out with respect to the relay (an export
condition). Relay Word bit ZLIN indicates that load is flowing in with respect
to the relay (an import condition). Figure 3.95 illustrates load-encroachment
settings and corresponding characteristics in the positive-sequence impedance
plane. Either Relay Word bit ZLOUT or ZLIN asserts if the relay measures a
positive-sequence impedance that lies within the corresponding hatched
region. Relay Word bit ZLOAD is the OR combination of ZLOUT and ZLIN.
Figure 3.94 Load-Encroachment Logic Diagram
Table 3.84 Series-Compensation Line Logic Relay Settings
Name Description Range
Default
(5 A)
ESERCMP Series-compensation line logic Y, N N
XC Series capacitor reactance () (OFF, 0.25–320
)/I
NOM
OFF
(Settin
g)
(Settin
g)
(Settin
g)
(Settin
g)
Pos.-Se
q.
V
1
Z
ZL
O
A
D
I
1L
Thr
es
h
o
l
d
NLAR > Z
1
>
PLAR
PLAF > Z
1
>
NLAF
ZLR
ZLF
ZL
OUT
Rela
y
W
o
r
d
Bi
ts
ZLIN
Pos.-Se
q
. Threshold = 0.1
•
I
n
om
L
oad
Out
L
oad
I
n
(Settin
g)
(Settin
g)
+
–
+
–
+
–