Sel 411L - Figure 3.32 External Fault Detection Logic-Communications

P.3.58
SEL-411L Relay Protection Manual Date Code 20151029
Protection Functions
87L Differential Elements
Figure 3.32 External Fault Detection Logic—Communications
The external fault detection logic is fully integrated with the 87L elements.
First, the 87EFD Relay Word bit forces the 87L elements to switch to
enhanced security settings (see Extended Security Setting Switchover Logic
for more details). Second, the 87EFD bit boosts the restraining action of the
87L elements by increasing the restraining terms that feed the generalized
Alpha Plane calculations (see 87L Theory of Operation for more information
on the generalized Alpha Plane of the relay).
As Figure 3.33 shows, the logic adds second, fourth, and fifth harmonics in
the phase differential current to the fundamental frequency restraining term
with an effective gain of 2, as controlled by the factory constants 87PCT2E,
87PCT4E, and 87PCT5E. This operation counters the CT saturation errors to
a large degree. These errors present themselves as a distorted spurious
differential current, so adding harmonics in the differential current to the
restraining term improves security of the 87LP element.
In addition, the logic calculates the maximum phase-restraining term among
the A, B, and C phases, including the adaptive harmonic boost upon the
87EFD assertion. The logic adds a third of this maximum current (controlled
by the factory constant 87kPQ = 0.33) to the fundamental frequency-
restraining term of the 87LQ element prior to executing the generalized Alpha
Plane calculations. This improves security upon CT saturation, especially for
three-phase balanced faults.
Similarly, the logic adds a third of the maximum phase-restraining current
(controlled by the factory constant 87kPG = 0.33) to the fundamental
frequency-restraining term of the 87LG element prior to executing the
generalized Alpha Plane calculations. This improves security upon CT
saturation, especially for three-phase balanced faults and phase-to-phase
faults.
From the Main
EFD Logic
87EFDAL
87EFDBL
87EFDCL
Relay Word Bit
87EFDL
Relay Word Bit
ESTUB
Relay Word Bit
87EFDR
EFD Received From
Remote Terminals,
all Required Channels
To Outgoing 87L Packets
(EFD bit)
Relay Word Bit
87EFD
Relay Word Bit
87TEST