Sel 411L - Figure 3.31 External Fault Detection Logic-DC Path

P.3.57
Date Code 20151029 Protection Manual SEL-411L Relay
Protection Functions
87L Differential Elements
Figure 3.31 External Fault Detection Logic—DC Path
The external fault logic lacks individual access to all remote currents. It
detects faults in the vicinity of the local terminal, but it may fail to trigger for
external faults close to the remote terminals, depending on the current flow at
the time. Therefore, the external fault detected bits are distributed among all
relay terminals in the 87L scheme.
As Figure 3.32 shows, the logic ORs the locally generated per-phase bits into
the 87EFDL Relay Word bit. If the relay is not in the stub bus mode (ESTUB
deasserted), the relay sends this bit to all remote relays in the 87L scheme. If
the relay is in stub bus mode, the local external fault concerns the local
differential zone that extends from the local CT (or CTs) to the opened line
disconnect switch; it does not concern the line differential zone the remote
relays maintain, so the logic will assert an interlock for that zone with
!ESTUB.
The logic ORs received EFD bits into the 87EFDR Relay Word bit, signaling
that one or more remote relays detected an external fault. The logic then ORs
this bit with local external fault detection (87EFDL) if the relay is not in the
stub bus mode. If the relay is in stub bus mode, the remote external fault
concerns the line differential zone the remote relays maintain; it does not
concern the differential zone that extends from the local CT (or CTs) to the
opened line disconnect switch, so the logic will assert an interlock for that
zone with !ESTUB.
The 87EFD Relay Word bit signifies detection of an external fault in the
vicinity of the local line terminal, if the relay is in stub bus mode, or in the
vicinity of the protected line, if the relay is not in stub bus mode. This external
fault condition demands extra security from the local 87L elements.
The relay logic overrides the 87EFD bit if the 87L function is in the test mode
(87TEST asserted). This simplifies testing by removing the need to inject
current signals that follow the actual patterns of external versus internal faults.
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Φ = A, B, C
87IΦRSTM
87IΦDIFM
87kRD
87PWDC
IΦWFM
IΦWDCM
Relay Word Bit
87CTWL
87PXDC
IΦXDCM
IΦXFM
87kDC
Relay Word Bit
87CTXL
87kDC
3
cyc
1
cyc
87EFDΦDC
To the Main
EFD Logic
Calibration Settings
87kRD 0.5
87PWDC 0.2 pu (CT)
87PXDC 0.2 pu (CT)
87kDC 0.3