P.3.68
SEL-411L Relay Protection Manual Date Code 20151029
Protection Functions
87L Differential Elements
Use the logic output Relay Word bits 87OCTA, 87OCTB, 87OCTC, and 87OCT to
implement your own strategy for open CT detection. Use the logic output Relay
Word bits 87ROCTA, 87ROCTB, 87ROCTC, 87ROCTU, and 87ROCT to
implement your own strategy for resetting an asserted open CT alert.
As Figure 3.39 shows, you enable the Open CT logic via the E87OCTL
setting, and the relay must be in the master mode (87MTR Relay Word bit
asserted) for the logic to be operational. In addition, detection of an external
fault (87EFD Relay Word bit asserted) inhibits the open CT logic.
The Open CT logic monitors changes in the differential and restraining
currents and checks whether the increase in the differential current matches
the decrease in the restraining current. If such a match exists, and other
conditions permit (as following text explains), the logic declares an open CT.
The logic monitors the absolute value of instantaneous differential current
(87IDIF) and the instantaneous restraining current (87IRST) for any
increase over the period of the last power cycle. It then adds together the two
values. Under open CT conditions, the change in the restraining signal is
negative and matches the positive changes in the differential signal, resulting
in a small sum. The logic checks whether the absolute value of the sum is less
than 1/8 of the absolute value of the change in the differential current. If so,
the increase in the differential signal matches the decrease in the restraining
signal and indicates an open CT condition.
Before the logic declares an open CT, it compares the change in the
differential signal with a portion of the averaged restraining signal to
determine whether the change in the differential signal is sufficiently
significant for reliable measurement and operation of the scheme. The logic
uses an IIR filter to average the full-cycle cosine-filtered restraining signal
(87IRSTM). The logic considers change in the differential signal reliable for
scheme operation if the change exceeds K
CT
times the average restraining
signal (factory constant 87KCT = 0.1).
Three more conditions supervise assertion of the open CT.
➤ The restraining signal must be sufficiently significant for the
logic to work. With no load current, the logic cannot reliably
match the increase in the differential signal with the decrease
in the restraining signal. The logic declares the restraining
signal sufficiently significant for scheme operation if the
averaged restraining current magnitude exceeds the 87
THR
threshold (the lesser of the 87LP pickup setting and 0.25 pu of
the 87L base).
➤ The standing differential current prior to the logic declaring an
open CT must be sufficiently low. The logic confirms this
condition by checking whether the full-cycle filtered
magnitude of the differential current (87IDIFM) is less than
half of the 87
THR
threshold.
The low differential signal and the significant restraining signal
conditions must coexist for five power cycles, indicating that
the system is in a quiescent and balanced condition, before the
logic can operate.
➤ The standing full-cycle filtered differential current when the
logic declares an open CT must be high compared with the
averaged restraining signal. A percentage slope of 5 percent or
15 percent used to perform this check depends on the
availability of charging current compensation.
To Next Page
Loading...
