Sel 411L - Page 24

xxii
SEL-411L Relay Date Code 20151029
List of Figures
Figure 2.31 Card Layout (Rear View of the Main Board).................................................................... P.2.38
Figure 2.32 Relay to Computer—D-Subminiature 9-Pin Connector ................................................... P.2.38
Figure 2.33 G.703 Card in the Bay 1 Position and a 850nm IEEE C39.94 Fiber Card in the
Bay 2 Position................................................................................................................ P.2.39
Figure 2.34 Typical EIA-422 Interconnection...................................................................................... P. 2. 40
Figure 2.35 Typical G.703 Codirectional Interconnection ................................................................... P.2.40
Figure 2.36 IEEE Standard C37.94 Fiber-to-Multiplexer Interface ..................................................... P.2.41
Figure 2.37 1300 nm Direct Fiber Connection..................................................................................... P.2.41
Figure 2.38 1550 nm Direct Fiber Connection..................................................................................... P.2.41
Figure 2.39 Four 100BASE-FX Port Configuration............................................................................. P.2.43
Figure 2.40 Four 10/100BASE-T Port Configuration .......................................................................... P.2.43
Figure 2.41 100BASE-FX and 10/100BASE-T Port Configuration..................................................... P.2.43
Figure 2.42 Typical External AC/DC Connections—Single Circuit Breaker ...................................... P.2.45
Figure 2.43 Typical External AC/DC Connections—Dual Circuit Breaker......................................... P.2.46
Figure 3.1 Sampling and Transmitting Instantaneous Local Currents in the 87L Scheme
(Breaker-and-a-Half Scheme).......................................................................................... P.3.5
Figure 3.2 Consolidating Currents in the 87L Scheme While Conserving the Channel Bandwidth............. P.3.5
Figure 3.3 Traditional Alpha Plane Operating Characteristic for 87L Zone With Two Currents ........ P.3.7
Figure 3.4 AC Saturation Path of the External Fault Detector (Simplified)....................................... P.3.10
Figure 3.5 Sharing the EFD Bits Among Relay Terminals ................................................................ P.3.11
Figure 3.6 DC Saturation Path of the External Fault Detector (Simplified)....................................... P.3.12
Figure 3.7 Illustration of Signal Processing for Line Charging Current Compensation .................... P.3.13
Figure 3.8 Admittance of a Sample Transmission Line as a Function of Frequency and
Line Length in Per-Unit of the Value at 60 Hz Differences Between the
Distributed Line and Its Lumped Parameter Model Can Lead to Under- or Over-
Compensation of the Charging Current......................................................................... P.3.15
Figure 3.9 The Under- or Over-Compensated High-Frequency Components of the Charging
Current Are Taken Care of by Boosting the Fundamental Frequency Restraining Term..........P.3.15
Figure 3.10 A Combined Transformer and Line Zone Protected With a Single Line Differential Relay
Capable of Handling In-Line Transformers (a), With Dedicated Transformer and
Line Relays (b), and With the Primary Protection Following the Dedicated Relay
Approach While the Backup Protection Uses a Single 87L Relay (c).................................. P.3.16
Figure 3.11 Compensation for In-Line Transformers is Performed at Early Stages of Signal
Processing, Allowing the Rest of the Algorithm to Remain Unchanged ...................... P.3.17
Figure 3.12 The Relay Allows Different Transformer Windings for each Measured CT (a) as
Well as Dual-Breaker Terminations of the In-Line Transformer Windings (b)............. P.3.18
Figure 3.13 Principle of Harmonic Restraint in the Generalized Alpha Plane Operating
Characteristic................................................................................................................. P. 3.19
Figure 3.14 Illustration of the Channel-Based Synchronization Method............................................. P.3.21
Figure 3.15 Application of Disturbance Detection in the Relay .......................................................... P.3.25
Figure 3.16 Local (87DDL) and Remote (87DDR) Disturbance Detection Harmonized With the
Stub Bus (ESTUB) and Test (87TEST) Conditions...................................................... P.3.25
Figure 3.17 Adaptive Disturbance Detector Algorithm........................................................................ P.3.26
Figure 3.18 Disturbance Detection Guards Against Multiple Problems Greatly Increasing
Security.......................................................................................................................... P.3.27
Figure 3.19 87LP Phase Differential Element Logic............................................................................ P.3.33
Figure 3.20 Overcurrent Supervision Logic for Line Current Differential Elements (Use With
Logic Diagrams in Figure 3.19, Figure 3.22, and Figure 3.23)..................................... P.3.34
Figure 3.21 Alpha Plane Comparator Logic for Line Current Differential Elements (Use With
Logic Diagrams in Figure 3.19, Figure 3.22, and Figure 3.23)..................................... P.3.34
Figure 3.22 87LQ Negative-Sequence Differential Element Logic ..................................................... P.3.37
Figure 3.23 87LG Zero-Sequence Differential Element Logic............................................................ P.3.40
Figure 3.24 87OP Logic ....................................................................................................................... P.3.42
Figure 3.25 87DTT Transmit Logic ..................................................................................................... P.3.46
Figure 3.26 87DTT Logic..................................................................................................................... P.3.47
Figure 3.27 Interaction Between Debounce Timing and Fail-Safe Substitution in the
User-Programmable 87L Bits Logic.............................................................................. P.3.49