Sel 411L - Page 28

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SEL-411L Relay Date Code 20151029
List of Figures
Figure 3.193 Enable Logic for the 87L Data Transmission and Differential Elements ....................... P.3.281
Figure 3.194 Blocking Logic for the 87L Function.............................................................................. P.3.281
Figure 3.195 87CHpRQ Logic for the 2SS and 3SM 87L Configurations........................................... P.3.283
Figure 3.196 87CHpRQ Logic for the 2SD 87L Configuration........................................................... P.3.284
Figure 3.197 Synchronization Method Logic (p-th Channel) .............................................................. P.3.289
Figure 3.198 Quality of Synchronization Logic (p-th Channel)........................................................... P.3.290
Figure 3.199 Quality of Synchronization Logic (87L Scheme) ........................................................... P.3.290
Figure 3.200 Maximum Round-Trip Delay Alarm Logic .................................................................... P.3.292
Figure 3.201 Step Change in Round-Trip Delay Logic........................................................................ P.3.293
Figure 3.202 Channel Asymmetry Alarm Logic.................................................................................. P.3.294
Figure 3.203 Lost Packet Alarm Logic................................................................................................. P.3.295
Figure 3.204 Noise Burst Alarm Logic ................................................................................................ P.3.295
Figure 3.205 Momentary Channel Break Alarm Logic........................................................................ P.3.295
Figure 3.206 Channel OK Status.......................................................................................................... P.3.296
Figure 3.207 Default Channel Alarm Logic......................................................................................... P.3.2 96
Figure 3.208 Principle of Hot Standby Channel Switching ................................................................. P.3.298
Figure 3.209 Channel Switchover Logic (87HSB)............................................................................... P.3.299
Figure 3.210 Request for Time Fallback From the p-th 87L Channel.................................................. P.3.302
Figure 3.211 Time Fallback Mode 1 Logic .......................................................................................... P.3. 302
Figure 3.212 Time Fallback Mode 2 Logic .......................................................................................... P.3. 303
Figure 3.213 Time Fallback Modes 3 and 4 Logic............................................................................... P.3.305
Figure 3.214 87L Master (87MTR) Logic............................................................................................ P. 3.307
Figure 3.215 87L Outstation (87SLV) Logic........................................................................................ P. 3.307
Figure 3.216 87L Lost (87LST) Logic................................................................................................. P.3.308
Figure 3.217 COM 87L Report Layout................................................................................................ P.3.310
Figure 3.218 500 kV Overhead Transmission Line.............................................................................. P.3.316
Figure 3.219 Channel Report During Commissioning Testing ............................................................ P.3.320
Figure 3.220 345 kV Overhead Tapped Line With In-Line Transformer............................................. P.3.332
Figure 3.221 CT Saturation Plot........................................................................................................... P.3.337
Figure 3.222 Various Overcurrent Elements Used in this Example..................................................... P.3.339
Figure 4.1 Autoreclose State Diagram for Circuit Breaker 1............................................................... P.4.4
Figure 4.2 Multiple Circuit Breaker Arrangement ............................................................................. P.4.15
Figure 4.3 Multiple Circuit Breaker Arrangement ............................................................................. P.4.18
Figure 4.4 Leader/Follower Selection by Relay Input........................................................................ P.4.22
Figure 4.5 Circuit Breaker Pole-Open Logic Diagram....................................................................... P.4.27
Figure 4.6 Line-Open Logic Diagram When E79 := Y...................................................................... P.4.27
Figure 4.7 Line-Open Logic Diagram When E79 := Y1.................................................................... P.4.27
Figure 4.8 Single-Pole Reclose Enable .............................................................................................. P.4.28
Figure 4.9 Three-Pole Reclose Enable ............................................................................................... P.4.28
Figure 4.10 One Circuit Breaker Single-Pole Cycle State (79CY1) .................................................... P.4.29
Figure 4.11 One Circuit Breaker Three-Pole Cycle State (79CY3)..................................................... P.4.30
Figure 4.12 Two Circuit Breakers Single-Pole Cycle State (79CY1) When E79 := Y........................ P.4.31
Figure 4.13 Two Circuit Breakers Single-Pole Cycle State (79CY1) When E79 := Y1...................... P.4.33
Figure 4.14 Two Circuit Breakers Three-Pole Cycle State (79CY3) When E79 := Y......................... P.4.35
Figure 4.15 Two Circuit Breakers Three-Pole Cycle State (79CY3) When E79 := Y1....................... P.4.38
Figure 4.16 Manual Close Logic.......................................................................................................... P.4.42
Figure 4.17 Voltage Check Element Applications................................................................................ P.4.44
Figure 4.18 Voltage Check Element Logic........................................................................................... P.4.45
Figure 4.19 Partial Breaker-and-a-Half or Partial Ring-Bus Breaker Arrangement............................. P.4.49
Figure 4.20 Synchronism-Check Voltages for Two Circuit Breakers................................................... P.4.50
Figure 4.21 Synchronism-Check Settings ............................................................................................ P.4.51
Figure 4.22 Synchronism-Check Relay Word Bits............................................................................... P.4.51
Figure 4.23 Example Synchronism-Check Voltage Connections to the Relay..................................... P.4.53
Figure 4.24 Synchronism-Check Voltage Reference............................................................................ P.4.54
Figure 4.25 Normalized Synchronism-Check Voltage Sources VS1 and VS2..................................... P.4.55
Figure 4.26 Healthy Voltage Window and Indication........................................................................... P.4.56
Figure 4.27 Synchronism-Check Enable Logic.................................................................................... P.4.56
Figure 4.28 “No Slip” System Synchronism-Check Element Output Response.................................. P.4.58