Sel 411L - Page 162

P.3.54
SEL-411L Relay Protection Manual Date Code 20151029
Protection Functions
87L Differential Elements
The external fault detection logic, the disturbance detection logic, and the
enhanced settings switchover logic are fully integrated with the 87L elements
and need no setting. The open CT logic is a stand-alone element that by
default neither blocks nor otherwise controls sensitivity of the 87L elements.
This is to accommodate diverse philosophies regarding treatment of an open
CT condition. Minimum settings are necessary to enable the logic, define the
reset condition, and determine the necessary action upon the logic detecting
an open CT condition.
External Fault Detection Logic
The external fault detection logic maintains the security of the 87L function
during external faults that can cause CT saturation. Such faults include high
fault currents or faults with a long-lasting decaying dc component in the
current.
The scheme, which 87L Theory of Operation describes briefly, is fully
integrated with the 87L elements and needs no setting. This section will assist
you in understanding logic details, such as when testing the 87L elements for
performance.
The external fault detection logic consists of five key elements.
➤ Detection of external faults accompanied by high ac
components in the 87L currents (“AC path,” Figure 3.30).
➤ Detection of external faults accompanied by high and long-
lasting dc components in the 87L currents (“DC path,”
Figure 3.31).
➤ Seal-in logic to maintain the external fault detected condition
and to allow reset when appropriate (Figure 3.30).
➤ Communications scheme to distribute the external fault
detected information to all relay terminals (Figure 3.32).
➤ Integration logic with the 87L elements to enhance their
security while maintaining dependability for evolving faults
after the external fault detection logic asserts (Figure 3.33).
The logic performs external fault detection, seal-in, and reset on a per-phase
basis ( stands for the phase index A, B, or C), while the distribution to
remote terminals and control of the 87L elements occurs for all three phases
regardless of the phase in which the logic has detected the external fault.
The external fault detection logic is fully symmetrical; all relays in the master
mode respond similarly regardless of the fault location with respect to any
given relay.
As Figure 3.30 shows, the logic monitors the instantaneous differential current
(87IDIF) for a change from its one-power-cycle-old value. The logic
performs this operation on a sample-by-sample basis and yields an
instantaneous response to an elevated differential current.
Similarly, the logic monitors instantaneous restraining current (87IRST) for
a change from its one-power-cycle-old value. This instantaneous restraining
current is the sum of absolute values of the local currents of the 87L zone and
remote line currents that the local relay receives from peer relays. This current
therefore reflects the through-fault conditions for external faults in the vicinity
of the local relay.