P.3.55
Date Code 20151029 Protection Manual SEL-411L Relay
Protection Functions
87L Differential Elements
The logic uses a factory constant of 0.75 pu of the 87L base (87DIRTR) to
qualify the change in the instantaneous restraining current. This means that
the "AC path" of the external fault detection logic can trigger if the
instantaneous restraining current increases by more than 0.75 pu. The logic
does not consider events failing to increase the restraint by more than 0.75 pu
to be causes of CT saturation resulting from AC component.
The logic compares the change in the differential current against a portion of
the change in the restraining current. For internal faults, the change in the
differential current approximately equals the change in the restraining current
(DIF = 100% • RST). For non-internal faults, the logic assumes the CTs are
working correctly for some time into a fault, and the differential current does
not increase (DIF = 0% • RST).
If the change in the differential current is less than half the change in the
restraining current (factory constant 87kRD = 0.5) for 3/16 of a power cycle,
the logic declares an external fault by the “AC path” of the external fault
detector.
Note that the logic will not trigger on internal faults even if CTs saturate, but it
will trigger on external faults with or without CT saturation.
Because the fault is transient in nature, the logic applies two dropout timers to
maintain the original external fault detection. The short, 87EXFMD, timer
ensures that the logic maintains the external fault detection for at least three
power system cycles. With the long, 87EXFDO, timer set to 60 power cycles,
the relay can ride through fast autoreclosing cycles.
It is possible to cancel the long timer if conditions allow. Resetting 87EXFDO
restores the original sensitivity of the 87L elements so that they respond faster
to evolving external-to-internal faults.
The reset condition has a three-cycle pickup timer for security that can time
out only if the logic has already detected an external fault (the feedback line in
Figure 3.30). The reset logic checks for expiration of the elevated fault current
event by comparing the magnitude of the filtered restraining current
(87IRSTM) with a factory constant of 0.2 pu of the 87L base (87EXFIR).
In addition, the reset logic checks if the differential current and harmonics in
the differential current are low in comparison to the restraining current. The
logic sums the magnitudes of the second, fourth, and fifth harmonics in the
differential current and compares these magnitudes with a portion of the
filtered restraining current (87kEXF = 0.1). If the differential current is less
than 10 percent of the restraint and has a low level of harmonics, suggesting
unsaturated CTs, the logic allows reset.
The reset logic further requires that the restraining current be more than
0.2 pu, that differential be higher than 10 percent of the restraining current,
and that the sum of harmonics in the differential current be higher than 10
percent of the restraining current for one power cycle to indicate that CT
saturation did occur.
The term reset applies to cancellation of the 60-cycle dropout timer,
87EXFDO. The three-cycle timer, 87EXFMD, is always in effect, and both
the “AC path” and “DC path” of the detection algorithm can retrigger to
secure the 87L elements even following cancellation of the long timer after
detection of the previous external fault.
To Next Page
Loading...
