RM0367 Rev 7 197/1043
RM0367 Reset and clock control (RCC)
225
7.3.7 Clock interrupt clear register (RCC_CICR)
Address: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Bit 2 HSI16RDYF: HSI16 ready interrupt flag
This bit is reset by software by writing the HSI16RDYC bit. It is set by hardware when the
HSE clock becomes stable and the HSI16RDYIE is set.
0: No clock ready interrupt caused by HSI16 clock failure
1: Clock ready interrupt caused by HSI16 clock failure
Bit 1 LSERDYF: LSE ready interrupt flag
This bit is reset by software by writing the LSERDYC bit. It is set by hardware when the LSE
clock becomes stable and the LSERDYIE is set.
0: No clock ready interrupt caused by LSE clock failure
1: Clock ready interrupt caused by LSE clock failure
Bit 0 LSIRDYF: LSI ready interrupt flag
This bit is reset by software by writing the LSIRDYC bit. It is set by hardware when the LSI
clock becomes stable and the LSIRDYIE is set.
0: No clock ready interrupt caused by LSI clock failure
1: Clock ready interrupt caused by LSI clock failure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res.
CSS
HSEC
CSS
LSEC
HSI48
RDYC
MSI
RDYC
PLL
RDYC
HSE
RDYC
HSI16
RDYC
LSE
RDYIC
LSI
RDYC
wwwwwww w w
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 CSSHSEC: Clock Security System Interrupt clear
This bit is set by software to clear the CSSHSEF flag. It is reset by hardware.
0: No effect
1: CSSHSEF flag cleared
Bit 7 CSSLSEC: LSE Clock Security System Interrupt clear
This bit is set by software to clear the CSSLSEF flag. It is reset by hardware.
0: No effect
1: CSSLSEF flag cleared
Bit 6 HSI48RDYC: HSI48 ready Interrupt clear
This bit is set by software to clear the HSI48RDYF flag. It is reset by hardware.
0: No effect
1: HSI48RDYF flag cleared
To Next Page
Loading...
Need help?
General
