Reset and clock control (RCC) RM0367
174/1043 RM0367 Rev 7
7.1.2 Power reset
A power reset is generated when one of the following events occurs:
• Power-on/power-down reset (POR/PDR reset)
• BOR reset
A power reset sets all registers to their reset values including for the RTC domain (see
Figure 16)
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map. For
more details, refer to Table 55: List of vectors.
The system reset signal provided to the device is output on the NRST pin (except the Exit
from Standby reset which is not output on the NRST pin but generates system reset).
The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal
reset source. In case of an external reset, the reset pulse is generated while the NRST pin is
asserted low.
When an internal reset occurs, the internal pull-up resistor (RPU) is deactivated in order to
save the power consumption through the pull-up resistor.
Figure 16. Simplified diagram of the reset circuit
7.1.3 RTC and backup registers reset
The RTC peripheral, RTC clock source selection (in RCC_CSR) and the backup registers
are reset only when one of the following events occurs:
• A software reset, triggered by setting the RTCRST bit in the RCC_CSR register (see
Section 7.3.21)
• Power reset (BOR/POR/PDR).
MSv41924V2
External
reset
V
DD
R
PU
WWDG reset
Firewall reset
Software reset
Low-power manager reset
IWDG reset
Option byte loader reset
BOR reset
Pulse
generator
(min 20 μs)
NRST
System reset
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