ST STM32L0x3 User Manual

Reset and clock control (RCC) RM0367
192/1043 RM0367 Rev 7
7.3.4 Clock configuration register (RCC_CFGR)
Address offset: 0x0C
Reset value: 0x0000 0000
Access: 0
≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. MCOPRE[2:0] MCOSEL[3:0] PLLDIV[1:0] PLLMUL[3:0] Res.
PLL
SRC
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOP
WUCK.
Res. PPRE2[2:0] PPRE1[2:0] HPRE[3:0] SWS[1:0] SW[1:0]
rw rw rw rw rw rw rw rw rw rw rw r r rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler
These bits are set and cleared by software.
It is highly recommended to change this prescaler before MCO output is enabled.
000: MCO is divided by 1
001: MCO is divided by 2
010: MCO is divided by 4
011: MCO is divided by 8
100: MCO is divided by 16
Others: not allowed
Bits 27:24 MCOSEL[3:0]: Microcontroller clock output selection
These bits are set and cleared by software.
0000: MCO output disabled, no clock on MCO
0001: SYSCLK clock selected
0010: HSI16 oscillator clock selected
0011: MSI oscillator clock selected
0100: HSE oscillator clock selected
0101: PLL clock selected
0110: LSI oscillator clock selected
0111: LSE oscillator clock selected
1000: HSI48 oscillator clock selected
Others: reserved
Note: This clock output may have some truncated cycles at startup or during MCO clock
source switching.
Bits 23:22 PLLDIV[1:0]: PLL output division
These bits are set and cleared by software to control PLL output clock division from PLL VCO
clock. These bits can be written only when the PLL is disabled.
00: not allowed
01: PLL clock output = PLLVCO / 2
10: PLL clock output = PLLVCO / 3
11: PLL clock output = PLLVCO / 4

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English