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General-purpose timers (TIM21/22) RM0367

580/1043 RM0367 Rev 7

The counter starts counting on the internal clock, then behaves normally until TI1 rising

edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the

trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if

enabled (depending on the TIE bit in TIMx_DIER register).

The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.

The delay between the rising edge on TI1 and the actual reset of the counter is due to the

resynchronization circuit on TI1 input.

Figure 187. Control circuit in reset mode

Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.

In the following example, the upcounter counts only when TI1 input is low:

1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration

(in this example, we do not need any filter, so we keep IC1F=’0000’). The capture

prescaler is not used for triggering, so it does not need to be configured. The CC1S bits

select the input capture source only, CC1S=’01’ in TIMx_CCMR1 register. Program

CC1P=’1’ and CC1NP= ‘0’ in TIMx_CCER register to validate the polarity (and detect

low level only).

2. Configure the timer in gated mode by writing SMS=’101’ in TIMx_SMCR register.

Select TI1 as the input source by writing TS=’101’ in TIMx_SMCR register.

3. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register (in gated mode, the

counter doesn’t start if CEN=’0’, whatever is the trigger input level).

For code example, refer to A.11.13: Gated mode code example.

The counter starts counting on the internal clock as long as TI1 is low and stops as soon as

TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts

or stops.

The delay between the rising edge on TI1 and the actual stop of the counter is due to the

resynchronization circuit on TI1 input.

MS31401V2

Counter clock = ck_cnt = ck_psc

Counter register

01 02 03 00 01 02 0332 33 34 35 36

TI1

3130

TIF

ST STM32L0x3 User Manual

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