ST STM32L0x3 - Figure 209. Window Watchdog Timing Diagram

RM0367 Rev 7 647/1043
RM0367 System window watchdog (WWDG)
650
Figure 209. Window watchdog timing diagram
The formula to calculate the timeout value is given by:
where:
t
WWDG
: WWDG timeout
t
PCLK
: APB1 clock period measured in ms
4096: value corresponding to internal divider
As an example, if APB1 frequency is 32 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63:
Refer to the datasheet for the minimum and maximum values of t
WWDG
.
For code example, refer to A.14.1: WWDG configuration code example.
MS47266V1
W[6:0]
0x3F
0x41
0x40
0x3F
wwdg_ewit
wwdg_rst
Refresh not allowed Refresh allowed
Time
T[6:0]
T
pclk
x 4096 x 2
WDGTB
CNT DownCounter
T6 bit
EWIF = 0
t
WWDG
t
PCLK1
4096 2
WDGTB[1:0]
T5:0[]1+()×××=ms()
t
WWDG
1 32000⁄()4096 2
3
×× 63 1+()× 65.54ms==