System and memory overview RM0367
56/1043 RM0367 Rev 7
2 System and memory overview
2.1 System architecture
The main system consists of:
• Two masters:
–Cortex
®
-M0+ core (AHB-lite bus)
– GP-DMA (general-purpose DMA)
• Three slaves:
– Internal SRAM
– Internal Non-volatile memory
– AHB to APB, which connects all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 1:
Figure 1. System architecture
1. Refer to Table 1: STM32L0x3 memory density, to Table 2: Overview of features per category and to the device datasheets
for the GPIO ports and peripherals available on your device.
MS32790V2
Busmatrix
APB buses
MIF
Memory interface
SRAM
AHB2APB
Bridges
Cortex
M0+
DMA
Controller
(Channels
1 to 7)
System bus
DMA
AES
AHB bus
Reset and
clock
controller
(RCC)
Touch
sensing
controller
(TSC)
CRC
DMA request
GPIO ports
A,B,C,D,E,H
NVM memory
RNG
SYSCFG
FIREWALL
PWR
CRS
EXTI
ADC
DAC
COMP1/2
TIM2/3/6/7/21/22
LPTIM1
IWDG
WWDG
RTC
DBGMCU
I2C1/2/3
USART1/2/3/4/LPUART1
SPI1/2
USB SRAM
USB FS
LCD
IOPORT
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