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RM0367 Rev 7 337/1043

RM0367 Analog-to-digital converter (ADC)

352

14.12 ADC registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.

14.12.1 ADC interrupt and status register (ADC_ISR)

Address offset: 0x00

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. EOCAL Res. Res. Res. AWD Res. Res. OVR EOS EOC EOSMP ADRDY

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 Reserved, must be kept at reset value.

Bit 11 EOCAL: End Of Calibration flag

This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.

0: Calibration is not complete

1: Calibration is complete

Bit 10 Reserved, must be kept at reset value.

Bits 9:8 Reserved, must be kept at reset value.

Bit 7 AWD: Analog watchdog flag

This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR

0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by

software)

1: Analog watchdog event occurred

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 OVR: ADC overrun

This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete

while the EOC flag was already set. It is cleared by software writing 1 to it.

0: No overrun occurred (or the flag event was already acknowledged and cleared by software)

1: Overrun has occurred

Bit 3 EOS: End of sequence flag

This bit is set by hardware at the end of the conversion of a sequence of channels selected by the

CHSEL bits. It is cleared by software writing 1 to it.

0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by

software)

1: Conversion sequence complete

ST STM32L0x3 User Manual

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