Reset and clock control (RCC) RM0367
182/1043 RM0367 Rev 7
7.2.6 LSE clock
The LSE crystal is a 32.768 kHz low speed external crystal or ceramic resonator. It has the
advantage of providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off through the LSEON bit in the RCC_CSR register
(see Section 7.3.21).
The crystal oscillator driving strength can be changed at runtime through the LSEDRV[1:0]
bits of the RCC_CSR register to obtain the best compromise between robustness and short
start-up time on one hand and low power consumption on the other hand. The driving
capability should be changed dynamically to determine the driving level that best matches
the used crystal. In the final application, it is then recommended to program this value in
LSEDRV[1:0] bits.
The LSERDY flag in the RCC_CSR register indicates whether the LSE crystal is stable or
not. At startup, the LSE crystal output clock signal is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the RCC_CIER register (see
Section 7.3.5).
External source (LSE bypass)
In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the RCC_CSR
(see Section 7.3.1). The external clock signal (square, sinus or triangle) with ~50% duty
cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left Hi-Z (see
Figure 40).
7.2.7 LSI clock
The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG). The clock frequency is around
37 kHz.
The LSI RC oscillator can be switched on and off using the LSION bit in the RCC_CSR
register (see Section 7.3.21).
The LSIRDY flag in RCC_CSR indicates whether the low-speed internal oscillator is stable
or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can
be generated if enabled in the RCC_CIER (see Section 7.3.5).
Since the IWDG is activated, the LSI oscillator cannot be stopped by LSION=0. The LSI
oscillator is stopped by system reset (except if IWDG is enabled by hardware option through
WDG_SW option bit in FLASH_OPTR register). If the IWDG was enabled by software, then
the LSI oscillator must be enabled again after system reset to ensure correct IWDG and/or
RTC operation.
LSI measurement
The frequency dispersion of the LSI oscillator can be measured to have accurate RTC time
base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an
acceptable accuracy. For more details, refer to the electrical characteristics section of the
datasheets. For more details on how to measure the LSI frequency, please refer to
Section 7.2.15: Internal/external clock measurement using TIM21.
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