Flash program memory and data EEPROM (FLASH) RM0367
104/1043 RM0367 Rev 7
master are blocked, the memory interface continues the operation freeing the bus and
the master.
• If the address is protected, the write/erase is filtered (the write/erase requested is never
sent to the memory) and an error is raised.
• If the address is not protected but one or several conditions are not met, the operation
is aborted (the abort needs more time to be executed because the NVM and data
EEPROM need to return to default configuration) and an error is raised.
• If the address to write/erase is not protected and all rules are respected, and if the
memory interface is busy, the operation is put on hold to be executed as soon as
possible.
Option byte loading
• If a write/erase is ongoing, the Option byte loading waits for the end of operation then it
is executed: no other write/erase is accepted, even if waiting.
• If no write/erase is ongoing, the Option byte is executed directly (the read operation is
executed until the system reset goes to 0 as a result of the Option byte request).
This means that the Option byte loading has a bigger priority than the read and write/erase
operations. All other operations are executed in the order of request.
3.6.2 Sequence of operations
Read as data while write
If the master requests a read as data (see Read as data and pre-read) while a write
operation is ongoing, there are three different cases:
1. If the read is in a protected area, the RDERR flag is raised and the write operation
continues.
2. If the write operation uses a Single programming operation or a Multiple programming
operation (half page) and all addresses/data have been sent to the memory interface,
any read operation from the same bank is put on hold and will be executed when the
write operation is complete. It is important to emphasize that, during all the time spent
when the read waits to be executed, the master is blocked and no other operation can
be executed until the write and read operations are complete. However, any authorized
read operation from the other bank is accepted and served.
3. if the write operation uses a Multiple programming operation (half page) and not all
addresses/data have been sent to the memory interface, the read operation is not
accepted whatever the targeted bank, a hard fault is generated and the memory
interface continues to wait for the missing addresses/data to complete the write
operation.
Fetch while write
If the master fetches an instruction while a write is ongoing, the situation is similar to a read
as data (see step 1 and 2 above), but the last case is as follows:
• If the write operation uses a Multiple programming operation (half page) and not all
addresses/data have been sent to the memory interface, the write is aborted and it is
as it had never happened: the read operation is accepted whatever the targeted bank,
and the value is sent to the master.
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