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Flash program memory and data EEPROM (FLASH) RM0367

82/1043 RM0367 Rev 7

When the memory interface receives the first address, it stalls the master for some pulses of

clock while it checks the protections and the previous value and it latches the new value

inside the NVM (for more details, see Table 17). Then, the memory interface waits for the

second address. No read is accepted: only a fetch will be executed, but it aborts the ongoing

write operation. After the second address, the memory interface stalls the core for a short

time (less than the previous one) to perform a check and to latch it in the NVM before

waiting for the next one. This sequence continues until all 16 words have been latched

inside the NVM. A wrong alignment or size will abort the write operation. If the 16 addresses

are correctly latched, the memory interface starts the write operation. The operation will

complete when EOP bit of FLASH_SR register rises (if it was 0 at the operation start). The

operation time is resumed in Table 19.

This protocol can be used either through application code running from RAM or through

DMA with application code running from RAM or core sleeping.

Unlocking/locking operations

Before performing a write/erase operation, it is necessary to enable it. The user can write

into the Flash program memory, data EEPROM and Option bytes areas.

To perform a write/erase operation, unlock PELOCK bit of the FLASH_PECR register. When

this bit is unlocked (its value is 0), the other bits of the same register can be modified. When

PELOCK is 0, the write/erase operations can be executed in the data EEPROM.

To write/erase the Flash program memory, unlock PRGLOCK bit of the FLASH_PECR

To write/erase the user Option bytes, unlock OPTLOCK bit of the FLASH_PECR register.

The bit can only be unlocked when PELOCK is 0. No relation exists between PRGLOCK

and OPTLOCK: the first one can be unlocked when the second one is locked and vice

versa.

Unlocking the data EEPROM and the FLASH_PECR register

After a reset, the data EEPROM and the FLASH_PECR register are not accessible in write

mode because PELOCK bit in the FLASH_PECR register is set. The same unlocking

sequence unprotects both of them at the same time.

The following sequence is used to unlock the data EEPROM and the FLASH_PECR

• Write PEKEY1 = 0x89ABCDEF to the FLASH_PEKEYR register

• Write PEKEY2 = 0x02030405 to the FLASH_PEKEYR register

For code example, refer to A.3.1: Unlocking the data EEPROM and FLASH_PECR register

code example.

ST STM32L0x3 User Manual

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