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ST STM32L0x3 User Manual

ST STM32L0x3
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Power control (PWR) RM0367
156/1043 RM0367 Rev 7
Exiting Low-power run mode
To exit Low-power run mode proceed as follows:
1. The regulator is forced in Main regulator mode by software.
2. The Flash memory is switched on, if needed.
3. The frequency of the clock system can be increased.
6.3.5 Entering low-power mode
Low-power modes (except for Low-power run mode) are entered by executing the WFI
(Wait For Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in
Cortex
®
-M0+ System Control register is set on Return from ISR.
Entering low-power mode through WFI or WFE will be executed only is no interrupt and no
event is pending.
6.3.6 Exiting low-power mode
The microcontroller exists from Sleep and Stop mode depending on the way the mode was
entered:
If the WFI instruction or Return from ISR was used to enter the low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device. This includes
EXTI lines and any GPIO toggle.
If the WFE instruction was used to enter low-power mode, the microcontroller exits the
low-power mode as soon as an event occurs. The wakeup event can be generated
either by:
An NVIC IRQ interrupt:
This is done by enabling an interrupt in the peripheral control register but not in the
NVIC, and by enabling the SEVONPEND bit in the Cortex
®
-M0+ System Control
register. When the microcontroller resumes from WFE, the peripheral interrupt
pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC
interrupt clear pending register) have to be cleared.
An event:
This is done by configuring an external or internal EXTI line in event mode. When
the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt
pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding
to the event line is not set.

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ST STM32L0x3 Specifications

General IconGeneral
BrandST
ModelSTM32L0x3
CategoryMicrocontrollers
LanguageEnglish

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