ST STM32L0x3 User Manual

Reset and clock control (RCC) RM0367
200/1043 RM0367 Rev 7
7.3.10 APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x24
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
Bits 19:17 Reserved, must be kept at reset value.
Bit 16
TSCRST: Touch Sensing reset
This bit is set and reset by software.
0: no effect
1: resets Touch sensing module
Bits 15: 13 Reserved, must be kept at reset value.
Bit 12 CRCRST: Test integration module reset
This bit is set and reset by software.
0: no effect
1: resets test integration module
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 MIFRST: Memory interface reset
This bit is set and reset by software.
This reset can be activated only when the E2 is in I
DDQ
mode.
0: no effect
1: resets memory interface
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 DMARST: DMA reset
This bit is set and reset by software.
0: no effect
1: resets DMA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res.
DBG
RST
Res. Res. Res. Res. Res. Res.
rw
1514131211109 8 7 6 543210
Res.
USART1
RST
Res.
SPI1
RST
Res. Res.
ADC
RST
Res. Res. Res.
TIM22
RST
Res. Res.
TIM21
RST
Res.
SYSCF
GRST
rw rw rw rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 DBGRST: DBG reset
This bit is set and cleared by software.
0: No effect
1: Resets DBG
Bits 21:15 Reserved, must be kept at reset value.

ST STM32L0x3 Specifications

General

Brand	ST
Model	STM32L0x3
Category	Microcontrollers
Language	English